PXR40RM Datasheet, PDF (1144/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
x(n)
Register
Coefficient 0
-1
Z
Tap0
Coefficient 1
-1
Z
Tap1
Coefficient 2
-1
Z
Tap2
Coefficient 3
-1
Z
Tap3
Coefficient 4
By-pass
00
A y(n)
+
+
Scale Factor S
Round/Sat
IIR
Round/Sat
FIR
01 _B 10
Coefficient 5
Coefficient 6
Coefficient 7
Coefficient 8
-1
Z
Tap4
-1
Z
Tap5
-1
Z
Tap6
-1
Z
Tap7
FTYPE[1:0]
Figure 28-15. Filter Configuration Paths (FIR or 1x4Poles IIR)
28.3.10 Rounding
The Decimation Filter performs rounding operations in two different locations, as shown in Figure 28-15:
• to obtain the filter output result with 16 bits
• to obtain the IIR feedback result to be stored in tap4 registers with 24 bits
The rounding mechanism implements the Convergent Rounding methodology (also known as
round-to-nearest even number), which makes the decision on rounding up or down based on the value of
the lower portion of data to be rounded (LS_WORD). The rounding up/down condition is equal to the
traditional rounding except when the LS_WORD has the format {1000...00}. In this particular case, the
rounding procedure is like the example of Figure 28-16. If the MS_WORD is odd, the value is rounded
up. Otherwise the value is rounded down.
28-30
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor