PXR40RM Datasheet, PDF (41/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Chapter 1
Introduction
The PXR40 device targets real-time, high performance applications. It is built upon the 90 nm CMOS
technology node. This document describes the features of the PXR40 and highlights important electrical
and physical characteristics of the device.
The e200z7 core of the PXR40 is compatible with the Power Architecture^® Book E architecture. It is 100%
user-mode compatible (with floating point library) with the classic PowerPC instruction set. The Book E
architecture has enhancements that improve the architecture’s fit in embedded applications. In addition to
the classic PowerPC instruction set, this core also has additional instruction support for digital signal
processing (DSP) and SIMD operations.
The PXR40 has two levels of memory hierarchy, a 32 KB Harvard architecture cache and a 256 KB
on-chip SRAM. 4 MB of internal flash memory is provided.
The features of the final, production-targeted device version are listed below.
1.1 PXR40 features
Table 1-1 shows the PXR40 feature set.
Core
SIMD
VLE
Cache
Feature
Non-maskable interrupt (NMI)
MMU
MPU
XBAR
Windowing software watchdog
Nexus
SRAM
Flash
Flash fetch accelerator
External bus
Calibration bus
DMA
DMA Nexus
Table 1-1. PXR40 feature set
PXR40
e200z7
Yes
Yes
32 KB
(16 KB Instruction/16 KB Data)
NMI & Critical Interrupt
64 entry
Yes
5×5
Yes
3+
256 KB
4 MB
4 × 256 bit
(first 1 MB of memory is 4 × 128; last 3 MB are 4 × 256)
Yes
16 bit non-muxed
32 bit muxed
96 channel
Class 3
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
1-1