PXR40RM Datasheet, PDF (1151/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
• DECFILTER_FINTVAL and DECFILTER_FINTCNT do not reset immediately; being updated
only upon a new output request (see Section 28.3.13.2, Integrator Output); if a integrator software
zero command (through SZRO bit) and an integrator output request (through SRQ bit) are made at
the same time, the registers DECFILTER_FINTVAL and DECFILTER_FINTCNT are updated
with the last internal values before reset; the same applies to simultaneous integrator zero
command and output request by hardware signal;
• all internal overflow flags
NOTE
An integrator zero request does not negate the SSOVF and SCOVF flags
NOTE
The integrator reset does not depend on the integrator enabling (see
Section 28.3.13.4, Integrator Enabling and Halting).
28.3.13.4 Integrator Enabling and Halting
Two mechanisms, enabling and halting, drive the integrator accumulation, allowing it to be controlled by
a combination of two sources:
• both software
• both hardware (eTPU2 channels)
• one hardware (eTPU2 channel) and other software
Values are accumulated when the integrator is enabled and not halted. The integrator halt and enable states
can be controlled in the following ways:
• by hardware, through eTPU2 channels; the enabling and the selection of the signal request modes
is done through DECFILTER_MXCR[SENSEL] and DECFILTER_MXCR[SHLTSEL] fields,
respectively (see Section 28.2.2.3, Decimation Filter Module Extended Configuration Register
(DECFILT_x_MXCR)), and channel selection is done through the SIU_DECFIL1 and
SIU_DECFIL2 and SIU_DECFIL3 registers in the SIU module.
• by software, through the same DECFILTER_MXCR[SENSEL] and
DECFILTER_MXCR[SHLTSEL] fields. Note that these fields are in different bytes, so that two
distinct, concurrent software tasks can avoid coherency problems by changing the fields using byte
read-modify-write accesses.
eTPU2 selection for the integrator enable state is defined by SIU_DECFILn[ZSELn] fields.
eTPU2 selection for the integrator halt state is defined by SIU_DECFILn[HSELn] fields.
NOTE
Enabling and halting does not affect output requests or integrator reset.
28.3.13.5 Integrator Exceptions
Integrator may run into exception states due to overflow, either of the accumulated value or the sample
counter. Exceptions are flagged by the DECFILTER_MXSR bits SSE, for sum value exception, and SCE,
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
28-37