PXR40RM Datasheet, PDF (796/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
Selected
Counter Bus
0x000020
Cycle n
Write to B2
Cycle (n + 1)
0x000001
A1 Value
A2 Value
B1 Value
B2 Value
0x000015
0x000015
0x000003
0x000003
Internal Time Base
0x000004
0x000004
Cycle (n + 2)
Time
0x000003
0x000001
Output Flip-Flop
Dead Time
Dead Time
Dead Time
Time
Figure 23-50. OPWMCB with 100% Duty Cycle (A1 = 4 and B1 = 3)
The output disable feature, if enabled, causes the output flip-flop to transition to the EDPOL inverted state.
This feature allows an application to force the channel output pin to a “safe” state. The internal channel
matches continue to occur even in this case, thus generating flags. As soon as the output disable is
deasserted, the channel output pin is again controlled by the A1 and B1 matches. This process is
synchronous, meaning that the output channel pin transitions on system clock edges only.
It is important to notice that, as in OPWMB and OPWFMB modes, the match signal used to set or clear
the channel output flip-flop is generated on the deassertion of the channel combinational comparator
output signal, which compares the selected time base with A1 or B1 register values. Refer to Figure 23-40,
which shows the delay from matches to output flip-flop transition in OPWFMB mode. The operation of
OPWMCB mode is similar to OPWFMB regarding matches and output pin transition.
23.4.1.1.17 Output Pulse Width Modulation (OPWM) Mode
In OPWM mode, registers A1 and B1 define the leading and trailing edges of the PWM output pulse,
respectively. The MODE[6] bit controls the transfer from register B2 to B1, which can be done either
immediately (MODE[6] cleared, MODE = 010_00b0), providing the fastest change in the duty cycle, or
at every match of register A1 (MODE[6] set, MODE = 010_00b1).
The value loaded in register A1 is compared with the value on the selected time base. When a match on
comparator A occurs, the output flip-flop is set to the value of the EDPOL bit. When a match occurs on
comparator B, the output flip-flop is set to the complement of the EDPOL bit.
FLAG can be generated at match B, when MODE[5] is cleared, or in both matches, when MODE[5] is set.
23-56
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor