PXR40RM Datasheet, PDF (870/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 25-5. DSPI_MCR Field Descriptions
Field
Description
0
MSTR
Master/Slave Mode Select. The MSTR bit configures the DSPI for either Master Mode or Slave Mode.
0 DSPI is in Slave Mode
1 DSPI is in Master Mode
1
Continuous SCK Enable. The CONT_SCKE bit enables the Serial Communication Clock (SCK) to run
CONT_SCKE continuously. See Section 25.4.8, Continuous Serial Communications Clock, for details.
0 Continuous SCK disabled
1 Continuous SCK enabled
2–3
DSPI Configuration. The DCONF field selects between the three different configurations of the DSPI.
DCONF[0:1] The values below list the DCONF values for the various configurations.
DCONF
00
01
10
11
DSPI Configuration
SPI
DSI
CSI
Reserved
4
FRZ
5
MTFE
6
PCSSE
7
ROOE
8–9
10–15
PCSISx
16
DOZE
Freeze. The FRZ bit enables the DSPI transfers to be stopped on the next frame boundary when the
device enters Debug Mode.
0 Do not stop serial transfers1Stop serial transfers
Modified Timing Format Enable. The MTFE bit enables a modified transfer format to be used. See
Section 25.4.7.4, Modified SPI/DSI Transfer Format (MTFE = 1, CPHA = 1), for more information.
0 Modified SPI transfer format disabled
1 Modified SPI transfer format enabled
Peripheral Chip Select Strobe Enable. The PCSSE bit enables the PCS[5]/PCSS to operate as an
PCS Strobe output signal. See Section 25.4.6.5, Peripheral Chip Select Strobe Enable (PCSS), for
more information.
0 PCS[5]/PCSS is used as the Peripheral Chip Select[5] signal
1 PCS[5]/PCSS is used as an active-low PCS Strobe signal
Receive FIFO Overflow Overwrite Enable. The ROOE bit enables an RX FIFO overflow condition to
either ignore the incoming serial data or to overwrite existing data. If the RX FIFO is full and new data
is received, the data from the transfer that generated the overflow is either ignored or shifted in to the
shift register. If the ROOE bit is asserted, the incoming data is shifted in to the shift register. If the
ROOE bit is negated, the incoming data is ignored. See Section 25.4.10.6, Receive FIFO Overflow
Interrupt Request, for more information.
0 Incoming data is ignored
1 Incoming data is shifted in to the shift register
Reserved, should be cleared
Peripheral Chip Select Inactive State. The PCSIS bit determines the inactive state of the PCSx signal.
0 The inactive state of PCSx is low
1 The inactive state of PCSx is high
Doze Enable. The DOZE bit provides support for externally controlled Doze Mode power-saving
mechanism. See Section 25.4.11, Power Saving Features, for details.
25-10
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor