PXR40RM Datasheet, PDF (743/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
23.1.2 Features
• 32 unified channels (UC)
• Channel features:
— 24-bit registers for captured/match values
— 24-bit internal counter
— Internal prescaler
— Selectable time base
— Can generate its own time base
• Five 24-bit-wide counter buses
— Counter bus A can be driven by unified channel 23or by the STAC bus.
— Counter buses B, C, D, and E are driven by unified channels 0, 8, 16, and 24, respectively
— Counter bus A can be shared among all unified channels. UCs 0 to 7, 8 to 15, 16 to 23, and 24
to 31 can share counter buses B, C, D, and E, respectively
• One global prescaler
• The output signal from the module configuration register’s global time base enable bit
(EMIOS_MCR[GTBE]) is wrapped back into the global timebase enable input so that the timebase
of each channel can be started simultaneously.
• Shared time bases through the counter buses
• Shadow FLAG register
• State of eMIOS200 can be frozen for debug purposes
• Debug mode is supported
23.1.3 Modes of Operation
There are three main operating modes of eMIOS200: run mode, module disable mode, and debug mode.
These modes are briefly described in this section.
Run mode is the normal operation mode and is described in Section 23.4, Functional Description.
Module disable mode is used for MCU power management. The clock to the non-memory-mapped logic
in the eMIOS200 is stopped while in module disable mode. Module disable mode is entered when
MDIS = 1 in the EMIOS_MCR.
Debug mode is individually programmed for each channel. When entering this mode, the unified channel
registers’ contents are frozen, but remain available for read and write access through the IP interface.
23.1.4 eMIOS200 Channel Configurations
Table 23-1 lists the eMIOS modes supported on the unified channels for this device. All included modes
are on all channels.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-3