PXR40RM Datasheet, PDF (780/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
boundary and therefore is used on cycle (n + 1). The cycle boundary between cycle (n) and cycle (n + 1)
is defined as the first system clock cycle of cycle (n + 1). The flags are generated as soon as the A1 match
occurs.
Prescaler Ratio = 1
Cycle n
Cycle n + 1
Cycle n + 2
EMIOS_CCNTR[n]
0x000007
0x000006
0x000005
Write to A2
A1 Match
Write to A2
A1 Match
A1 Match
0x000001
FLAG Set Event
FLAG Pin/Register
FLAG Clear
A2 Value
A1 Value
0x000006
0x000005
0x000007
0x000005
0x000007
Figure 23-34. Modulus Counter Buffered (MCB) Up Count Mode
Time
0x000007
Figure 23-35 shows the MCB in up/down counter mode. Register A1 is updated at the cycle boundary. If
A2 is written in cycle (n), this new value is used in cycle (n + 1) for an A1 match. When MODE[5] is
cleared, flags are generated only on an A1 match. If MODE[5] is set to 1, flags are also generated at the
cycle boundary.
Prescaler Ratio = 1
EMIOS_CCNTR[n]
0x000007
0x000006
0x000005
Cycle n
A1 Match
Write to A2
Cycle n + 1
A1 Match
Write to A2
Cycle n + 2
0x000001
FLAG Set Event
FLAG Pin/Register
FLAG Clear
A2 Value
A1 Value 0x000006
0x000005
0x000005
Figure 23-35. MCB Up/Down Mode
0x000007
0x000007
Time
Figure 23-36 shows the A1 register update process in up counter mode. The A1 load signal is generated at
the last system clock period of a counter cycle.
23-40
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor