PXR40RM Datasheet, PDF (1077/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
what should be done with the received data. The EQADC hardware decodes the MESSAGE_TAG and
DEST fields and:
• stores the 16-bit data into the appropriate RFIFO if the MESSAGE_TAG indicates a valid RFIFO
number and DEST value is zero, or;
• sends the 16-bit data, the MESSAGE_TAG and the non-zero DEST data through the PSI to an
on-chip companion module (as a decimation filter), or;
• ignores the data in case of a null or “reserved for customer use” MESSAGE_TAG and DEST value
is zero.
In general received data is moved into RFIFOs as they become available, while an exception happens when
multiple results from different sources become available at the same time. In that case, result data from
ADC0 is processed first, result data from ADC1 is only process after all ADC0 data is processed, and
finally returned data from the companion module is processed (after all data from ADC0/1 is processed).
When time-stamped results return from the on-chip ADCs, the conversion result and the time stamp are
always moved to the RFIFOs in consecutive clock cycles in order to guarantee they are always stored in
consecutive RFIFO entries.
27.7.6 On-Chip ADC Configuration and Control
27.7.6.1 Enabling and Disabling the On-chip ADCs
The on-chip ADCs have an enable bit (ADC0/1_EN) in the Section 27.6.3.1, ADC0/1 Control Registers
(ADC0_CR and ADC1_CR), which allows the enabling of the ADCs only when necessary. When the
enable bit for an ADC is negated, the clock input to that ADC is stopped. The ADCs are disabled out of
reset - ADC0/1_EN bits are negated - to allow for their safe configuration. The ADC must only be
configured when its enable bit is negated. Once the enable bit of an ADC is asserted, clock input to is
started.
NOTE
Conversion commands sent to the CBuffer of a disabled ADC are ignored
by the ADC control hardware.
NOTE
A 8ms wait time from VDDA power up to enabling ADC is required to
pre-charge the external 100nf capacitor on REFBYPC pin. This time must
be guaranteed by crystal startup time plus reset duration or user. The ADC
internal bias generator circuit will start up after 10us upon VRH/VRL and
VDDA/VSSA power up and produces a stable/required bias current to the
pre-charge circuit, but the current to other analog circuits are disabled until
ADCs are enabled. As soon as the ADCs are enabled, the bias currents to all
of analog circuits will be enabled.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-95