PXR40RM Datasheet, PDF (1422/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Device Performance Optimization
managed by tlbre, tlbwe, tlbsx, tlbsync, and tlbivax instructions. Refer to the core reference manual for
full details of the MMU and its configurations.
There are several MMU Assist Register registers (MAS0-3) that require configuring. Details of these are
provided in the e200z7 reference manual. Specifically, the MAS 2 register contains the fields to control
whether a specified memory region described by the valid TLB Entry is cache inhibited or whether VLE
encoding is valid.
EPN
V
0
LW I MGE
E
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 626; Read/Write
Figure 33-4. MMU Assist Register 2 (MAS2)
Table 33-4. MAS2 Register Field Descriptions
Field
0–21
EPN
22–25
26
VLE
27
W
28
I
29
M
30
G
31
E
Effective page number [0:21]
Description
Reserved
PowerPC VLE
0 - This page is a standard BookE page
1 - This page is a PowerPC VLE page
Write-through Required
Cache Inhibited
0 - This page is considered cacheable
1 - This page is considered cache-inhibited
Memory Coherence Required
Memory Coherence Required
Endianness
Refer to the e200z7 core reference manual for further details of MMU configuration registers.
33.4 Application Software
33.4.1 Compiler Optimizations
The most significant opportunity for influencing the performance of a given application is by compiler and
linker optimizations. Optimizing is a trade off between code size and performance. Typically higher
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
33-10