PXR40RM Datasheet, PDF (960/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
After the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter
returns to the Ready state via the done transition. If no frame or character transmit request is pending, the
transfer complete flag TC in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set.
If the application has disabled the transmitter while the preamble is transmitted and if the stop bit has been
transmitted, the transmitter goes into the Idle state via the halt transition. The transfer complete flag TC in
the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set and the internal commit bit iCMT is cleared.
26.4.5.2.7 Break Character Transmission
The transmission of a break character is started when the transmitter is in Ready state and the send break
character bit SBK in the Control Register 1 (eSCI_CR1) is set. After the transmission of the break
character and if the application has not disabled the transmitter, the transmitter returns to the Ready state
via the done transition and restarts the transmission. As long as SBK bit remains set, the transmitter
continues to send break characters.
When the application has cleared the SBK bit or has disabled the transmitter, the transmitter continues to
transmit the current break character and after it has finished the transmission of this break character it
transmits a stop bit. The stop bit at the end of a break character sequence guarantees the recognition of the
start bit of the next data frame.
After the transmission of the stop bit and if the application has not disabled the transmitter, the transmitter
returns to the Ready state via the done transition. If no frame or character transmit request is pending, the
transfer complete flag TC in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set.
If the application has disabled the transmitter while the break character is transmitted and if the stop bit
has been transmitted, the transmitter goes into the Idle state via the halt transition. The transfer complete
flag TC in the Interrupt Flag and Status Register 1 (eSCI_IFSR1) is set and the internal commit bit iCMT
is cleared.
26.4.5.3 Receiver
The receiver supports the reception of all data frame types defined in Table 26-18 and Table 26-19, of all
break character defined in Table 26-20, and of all idle characters defined in Table 26-21.
26.4.5.3.1 Receiver States and Transitions
The receiver has four basic states which are shown and described in Table 26-26. The state transitions that
can triggered by the application commands are shown in Table 26-26. The state transitions that can
triggered by the module are shown in Table 26-27. The state diagram of the transmitter is shown in
Figure 26-25.
26-32
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor