PXR40RM Datasheet, PDF (905/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Slave Bus Interface
Deserial Serial Peripheral Interface (DSPI)
TX FIFO
DSI Serialization ¹⁶
Data Register
Parallel 16
Inputs
(P_IN)
DSI Control
Register
Transfer
Priority
Logic
16
DSI Transmit
Comparison Register
16
Clock
Logic
01
15
Shift Register
SCK
SOUT
Control
Logic
PCSx (SPI)
PCSy (DSI)
Figure 25-25. CSI Serialization Diagram
The Parallel Inputs signal states are latched into the DSPI DSI Serialization Data Register (DSPI_SDR)
on the rising edge of every system clock and serialized based on the transfer initiation control settings in
the DSPI_DSICR. When SPI frames are written to the TX FIFO they have priority over DSI data from the
DSPI_SDR and are transferred at the next frame boundary. A copy of the most recently transferred DSI
frame is stored in the DSPI_COMPR. The Transfer Priority Logic selects the source of the serialized data
and asserts the appropriate CS signal.
25.4.5.2 CSI Deserialization
The deserialized frames in CSI Configuration goes into the DSPI_SDR or the RX FIFO based on the
transfer priority logic. When DSI frames are transferred the returned frames are deserialized and latched
into the DSPI_DDR. When SPI frames are transferred the returned frames are deserialized and written to
the RX FIFO. Figure 25-26 shows the CSI Deserialization logic.
Slave Bus Interface
Control
Logic
Transfer
Priority
Logic
RX FIFO
DSI Deserialization
16
Data Register
SIN
01
15
16
16
Parallel
Shift Register 16
Outputs
(P_OUT)
Figure 25-26. CSI Deserialization Diagram
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
25-45