PXR40RM Datasheet, PDF (611/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
Table 22-20. PIER1 Field Descriptions
Field
EMC_IE
IPC_IE
PECF_IE
PSC_IE
SSI3_IE
SSI2_IE
SSI1_IE
SSI0_IE
EVT_IE
ODT_IE
Description
Error Mode Changed Interrupt Enable — This bit controls EMC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Illegal Protocol Control Command Interrupt Enable — This bit controls IPC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Protocol Engine Communication Failure Interrupt Enable — This bit controls PECF_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Protocol State Changed Interrupt Enable — This bit controls PSC_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Slot Status Counter Incremented Interrupt Enable — This bit controls SSI[3:0]_IF interrupt request
generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Even Cycle Table Written Interrupt Enable — This bit controls EVT_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
Odd Cycle Table Written Interrupt Enable — This bit controls ODT_IF interrupt request generation.
0 interrupt request generation disabled
1 interrupt request generation enabled
22.5.2.15 CHI Error Flag Register (CHIERFR)
Base + 0x0020
Write: Normal Mode
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R FRLB FRLA PCMI FOVB FOVA MBS MBU LCK DBL SBCF FID DPL SPL NML NMF ILSA
_EF _EF _EF _EF _EF _EF _EF _EF _EF _EF _EF _EF _EF _EF _EF _EF
W w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c w1c
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-15. CHI Error Flag Register (CHIERFR)
This register holds the CHI related error flags. The interrupt generation for each of these error flags is
controlled by the CHI interrupt enable bit CHIE in the Global Interrupt Flag and Enable Register (GIFER).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-27