PXR40RM Datasheet, PDF (624/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
Field
MIF
PRIF
CHIF
WUPIF
FAFBIF
FAFAIF
RBIF
TBIF
Table 22-35. CIFRR Field Descriptions
Description
Module Interrupt Flag — This flag is set if there is at least one interrupt source that has its interrupt flag
asserted.
0 No interrupt source has its interrupt flag asserted
1 At least one interrupt source has its interrupt flag asserted
Protocol Interrupt Flag — This flag is set if at least one of the individual protocol interrupt flags in the Protocol
Interrupt Flag Register 0 (PIFR0) or Protocol Interrupt Flag Register 1 (PIFR1) is equal to 1.
0 All individual protocol interrupt flags are equal to 0
1 At least one of the individual protocol interrupt flags is equal to 1
CHI Interrupt Flag — This flag is set if at least one of the individual CHI error flags in the CHI Error Flag Register
(CHIERFR) is equal to 1.
0 All CHI error flags are equal to 0
1 At least one CHI error flag is equal to 1
Wakeup Interrupt Flag — Provides the same value as GIFER[WUPIF]
Receive FIFO Channel B Almost Full Interrupt Flag — Provides the same value as GIFER[FAFBIF]
Receive FIFO Channel A Almost Full Interrupt Flag — Provides the same value as GIFER[FAFAIF]
Receive Message Buffer Interrupt Flag — This flag is set if for at least one of the individual receive message
buffers (MBCCSRn[MTD] = 0) the interrupt flag MBIF in the corresponding Message Buffer Configuration,
Control, Status Registers (MBCCSRn) is equal to 1.
0 None of the individual receive message buffers has the MBIF flag asserted.
1 At least one individual receive message buffers has the MBIF flag asserted.
Transmit Message Buffer Interrupt Flag — This flag is set if for at least one of the individual single or double
transmit message buffers (MBCCSRn[MTD] = 1) the interrupt flag MBIF in the corresponding Message Buffer
Configuration, Control, Status Registers (MBCCSRn) is equal to 1.
0 None of the individual transmit message buffers has the MBIF flag asserted.
1 At least one individual transmit message buffers has the MBIF flag asserted.
22.5.2.30 System Memory Access Time-Out Register (SYMATOR)
Base + 0x003E
0
1
R0
0
W
Reset 0
0
Write: Disabled Mode
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
TIMEOUT
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Figure 22-30. System Memory Access Time-Out Register (SYMATOR)
Table 22-36. SYMATOR Field Descriptions
Field
TIMEOUT
Description
System Memory Access Time-Out — This value defines the maximum amount of time to finish a system bus
access in order to ensure correct frame transmission and reception (see Section 22.6.19.2, System Bus Access
Timeout).
22-40
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor