PXR40RM Datasheet, PDF (273/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
EIRQ pins
or
internal
source
SIU
SIU_EISR
••• ^IMUX •••
0
1
2
3
4
•••
•••
15
SIU_OSR
0
1
•••
•••
15
SIU_DISR
DMA/
interrupt
select
••
••
DMA
request
Interrupt
request
DMA
Interrupt
controller
Interrupt
request
Overrun
request
Figure 7-48. SIU DMA/Interrupt Request Diagram
7.4.4 GPIO Operation
All GPIO functions for the device are provided by the SIU. Each device pad that has a GPIO signal has a
pin configuration register (PCR) in the SIU where the GPIO function is selected. In addition, each device
GPIO signal has an input data register (SIU_GPDIn) and an output data register (SIU_GPDOn).
The SIU also implements several parallel GPIO registers (SIU_PGPDOx_x and SIU_PGPDIx_x) that can
be used to access up to 32 GPIO bits in a single- and word-sized accesses. The values read/written to these
parallel registers are coherent with the data read/written to the SIU_GPDOx_x and SIU_GPDIx_x
registers.
7.4.5 Internal Multiplexing
The internal multiplexing select registers (SIU_ISEL4-7, SIU_EIISR, and SIU_DISR) select the input
source for the following components:
• eQADC command FIFO trigger sources.
• SIU external interrupt request signals
• DSPI signals used for chaining serial and parallel DSPI modules
A block diagram of the internal multiplexing feature is shown in Figure 7-49. The figure shows the
multiplexing of four external signals to an SIU output.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-91