PXR40RM Datasheet, PDF (567/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
temporarily stored in the data path module until it is gated onto the system bus during the destination write.
This source read/destination write processing continues until the inner minor byte count has been
transferred. The eDMA done handshake signal is asserted at the end of the minor byte count transfer.
eDMA
SRAM
Transfer control descriptor
(TCD)
Slave write address
Slave write data
SRAM
TCD0
eDMA engine
Bus read data
Data path
Bus write data
Bus address
Program model/
channel arbitration
Address
path
Control
TCDn – 1*
Slave read data
*n = 32 (64 for eDMA_A) channels
eDMA peripheral eDMA interrupt request
request eDMA done handshake
Figure 21-26. eDMA Operation, Part 2
After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the address path logic performs the required updates to certain fields in the channel’s TCD;
for example, SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then there are
additional operations performed. These include the final address adjustments and reloading of the BITER
field into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a
possible fetch of a new TCD from memory using the scatter-gather address pointer included in the
descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in
Figure 21-27.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
21-43