PXR40RM Datasheet, PDF (623/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
22.5.2.28 Offset Correction Value Register (OFCORVR)
Base + 0x003A
0
1
R
W
Reset 0
0
Additional Reset: RUN Command
2
3
4
5
6
7
8
9
10
11
12
13
14
15
OFFSETCORR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-28. Offset Correction Value Register (OFCORVR)
This register provides the sign extended offset correction value in microticks as it was calculated by the
clock synchronization algorithm. The controller updates this register during the NIT.
Table 22-34. OFCORVR Field Descriptions
Field
OFFSET-
CORR
Description
Offset Correction Value — protocol related variable: vOffsetCorrection (before value limitation and external
offset correction)
This field provides the sign extended offset correction value in microticks as it was calculated by the clock
synchronization algorithm. The value is represented in 2’s complement format. This value does not include the
value limitation and the application of the external offset correction. If the magnitude of the internally calculated
rate correction value exceeds the limit given by offset_correction_out field in the Protocol Configuration Register
29 (PCR29), the clock correction reached limit interrupt flag CCL_IF is set in the Protocol Interrupt Flag Register
0 (PIFR0).
Note: If the controller was not able to calculate an new offset correction term due to a lack of synchronization
frames, the OFFSETCORR value is not updated.
22.5.2.29 Combined Interrupt Flag Register (CIFRR)
Base + 0x003C
0
1
R0
0
W
Reset 0
0
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
0
0
0
0
0
MIF
PRIF
CHIF
WUP
IF
FAFB
IF
FAFA
IF
RBIF
TBIF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 22-29. Combined Interrupt Flag Register (CIFRR)
This register provides five combined interrupt flags and a copy of three individual interrupt flags. The
combined interrupt flags are the result of a binary OR of the values of other interrupt flags regardless of
the state of the interrupt enable bits. The generation scheme for the combined interrupt flags is depicted in
Figure 22-152. The individual interrupt flags WUPIF, FAFBIF, and FAFAIF are copies of corresponding
flags in the Global Interrupt Flag and Enable Register (GIFER) and are provided here to simplify the
application interrupt flag check. To clear the individual interrupt flags, the application must use the Global
Interrupt Flag and Enable Register (GIFER).
NOTE
The meanings of the combined status bits MIF, PRIF, CHIF, RBIF, and
TBIF are different from those mentioned in the Global Interrupt Flag and
Enable Register (GIFER).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
22-39