PXR40RM Datasheet, PDF (177/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Frequency Modulated Phase-Locked Loop (FMPLL)
2. Write a value of ERFD = ERFD (from step 1) + 2 to the ERFD field of the ESYNCR2. Not
increasing the ERFD when changing the EPREDIV or EMFD could subject the device to clock
frequencies beyond the range specified for the device due to the PLL’s unlocked state.
3. If frequency modulation is currently enabled, disable it by writing 00 to the EDEPTH field of the
ESYNCR2.
4. If programming the EPREDIV and/or EMFD, write the value(s) determined in step 1 to the
appropriate field(s) in the ESYNCR1.
5. Monitor the synthesizer lock bit (LOCK) in the synthesizer status register (SYNSR). When the
PLL achieves lock, write the ERFD value determined in step 1 to the ERFD field of the ESYNCR2.
This changes the system clocks frequency to the desired frequency. If frequency modulation is
desired, leave ERFD programmed to ERFD + 2 until after completing the steps in
Section 6.4.3.4.2, Programming System Clock Frequency With Frequency Modulation.
6. If frequency modulation was enabled initially, it can be re-enabled following the steps listed in
Section 6.4.3.4.2, Programming System Clock Frequency With Frequency Modulation.
During startup, current transients on the VDD supply are related to the system frequency. A technique can
be used to reduce these current transients when the system frequency is changed from its default value to
your desired frequency.
Follow the above procedure for step 1. In step 2, rather than set ERFD to ERFD (from step 1) + 2, set this
to a value which will produce a low system frequency (close to the default system frequency), e.g.
ERFD = ERFD (from step 1) + 4. Once set, follow steps 3 and 4 as above. In step 5, wait for the LOCK
bit to set, then set the EFRD bit to ERFD (from step 2) – 2. Wait for a small duration of time for the current
to stabilize, then repeat this procedure until the ERFD value is equal to the value determined in step 1.
Using this technique you should observe the system frequency increasing in steps to the desired system
frequency. This results in the VDD current increasing to its equivalent final value in smaller current steps
which, therefore, produce smaller current transients, making it easier for the power supply to handle.
6.4.3.4 PLL Normal Mode With Frequency Modulation
In normal PLL clock mode, frequency modulation is not enabled in the default synthesis mode. When
frequency modulation is enabled several parameters must be set to generate the desired level of
modulation. The parameters to be programmed are the ERATE and EDEPTH bit fields of the ESYNCR2
register and the FMDAC_EN and FMDAC_CTL bits in the SYNFMCR register. The ERATE bit controls
the frequency of modulation, F_mod. The EDEPTH bits work in conjunction with the FMDAC_CTL bits in
the SYNFMCR to enable and control the modulation depth, F_m. The available modulation rates and depths
are given in Table 6-7 and Table 6-8, respectively. The modulation waveform is always a triangle wave
and its shape is not programmable. An example of one period of the modulation waveform is shown in
Figure 6-8.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
6-19