PXR40RM Datasheet, PDF (402/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
tlbwe
tlb write entry
tlbwe
31
0
56
0
1111010010
0
20 21
30 31
tlb_entry_id = MAS0(TLBSEL, ESEL)
MMU(tlb_entry_id) = MAS1, MAS2, MAS3
13.4.5 MMU Registers
13.4.5.1 DEAR Register
The Data Exception Address register is loaded with the effective address of the data access which results
in an Alignment, Data TLB Miss, or DSI exception.
Effective Page Address
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 61; Read/ Write; Reset - Unaffected
Figure 13-5. DEAR
The DEAR register can be read or written using the mfspr and mtspr instructions.
13.4.5.2 MMU Control and Status Register 0 (MMUCSR0)
The MMU Control and Status Register 0 (MMUCSR0) is a 32-bit register. The SPR number for
MMUCSR0 is 1012 in decimal. MMUCSR0 controls the state of the MMU. The MMUCSR0 register is
shown below.
0
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
SPR - 1012; Read/ Write; Reset - 0x0
Figure 13-6. MMU Control and Status Register 0 (MMUCSR0)
The MMUCSR0 bits are described below.
13-14
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor