PXR40RM Datasheet, PDF (60/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Introduction
• Zero padding for transmit message buffers in static segment
— Applied when the frame payload length exceeds the size of the message buffer data section
• Transmit message buffers configurable with state/event semantics
• Message buffers can be configured as
— Receive message buffer
— Single-buffered transmit message buffer
— Double-buffered transmit message buffer (combines two single buffered message buffer)
• Individual message buffer reconfiguration supported
— Means provided to safely disable individual message buffers
— Disabled message buffers can be reconfigured
• Two independent receive FIFOs
— One receive FIFO per channel
— As many as 255 entries for each FIFO
— Global frame ID filtering, based on both value/mask filters and range filters
— Global channel ID filtering
— Global message ID filtering for the dynamic segment
• Four configurable slot error counters
• Four dedicated slot status indicators
— Used to observe slots without using receive message buffers
• Measured value indicators for the clock synchronization
— Internal synchronization frame ID and synchronization frame measurement tables can be
copied into the FlexRay memory
• Fractional macroticks are supported for clock correction
• Maskable interrupt sources provided via individual and combined interrupt lines
• One absolute timer
• One timer that can be configured as absolute or relative
• Nexus data trace support
1.2.24 JTAG controller (JTAGC)
The JTAG controller (JTAGC) block provides the means to test chip functionality and connectivity while
remaining transparent to system logic when not in test mode. Testing is performed via a boundary scan
technique, as defined in the IEEE 1149.1-2001 standard. All data input to and output from the JTAGC
block is communicated in serial format. The JTAGC block is compliant with the IEEE 1149.1-2001 and
IEEE 1149.7 standards, and supports the following features:
• IEEE 1149.1-2001 Test Access Port (TAP) interface five pins (JCOMP, TDI, TMS, TCK, and
TDO)
• IEEE 1149.7 Serial JTAG Test Access Port interface three pins (JCOMP, TMS, TCK)
• A 5-bit instruction register that supports the following IEEE 1149.1-2001 defined instructions:
1-20
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor