PXR40RM Datasheet, PDF (446/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Peripheral Bridge (PBRIDGE)
• Require supervisor privilege level for access
• Restrict access to a trusted master only
• Write-protect the peripheral to deny updates to the peripheral (i.e., not all accesses are denied, reads
are still allowed)
Refer to Table 15-1 for a list of master/slave IDs and the peripherals for with each master and slave. The
shaded areas in the table do not apply.
Refer to Section 12.2.2.9, Flash Bus Interface Access Protection Register (FLASH_BIUAPR), in the Flash
chapter, for more information on access protection.
Table 15-1. Peripheral Bridge Master/Slave ID Table
Module
e200z7 core—CPU instruction
e200z7—Data
Nexus 3
eDMA_A
eDMA_B
FlexRay
On-chip Flash
External development bus (EBI)
On-chip SRAM
PBRIDGE A
Internal
Master ID
0
0
8
4
5
6
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
XBAR Port
Peripheral
Master 0
Master 1
Master 4
Master 5
Master 6
Slave 0
Slave 1
Slave 2
Slave 6
—
—
—
—
—
—
—
—
—
PBRIDGE A
FMPLL
EBI control
Flash control
SIU
eMIOS
PMC
eTPU reg
eTPU PRAM
eTPU PRAM mirror
eTPU SCM
PIT_RTI
15-2
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor