PXR40RM Datasheet, PDF (1176/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
• up to 32 channels for each eTPU Engine, each channel is associated with an Input/Output signal
pair.
— enhanced input digital filters on the input pins for improved noise immunity. The eTPU digital
filter can use 2 samples, 3 samples or work in continuous mode.
— identical, orthogonal channels, except for channel 0: each channel can perform any time
function. Each time function can be assigned to more than one channel at a given time, so each
signal can have any functionality. Channel 0 has the same capabilities of the others, but can also
work with special Angle Counter logic (see below).
— Link Service Request allows activation of a Channel function by request of another channel,
even between eTPU Engines.
— Host Service Request allows activation of a Channel function by Host CPU request
— each channel has an event mechanism which supports single and double action functionality in
various combinations. It includes two 24-bit capture registers, two 24-bit match registers,
24-bit greater-equal and equal-only comparators.
• Two independent 24-bit time bases for channel synchronization:
— first time base clocked by system clock with programmable prescaler division from 1 to 512
(in steps of 2), or by output of second time base prescaler.
— first time base can also be clocked by external signal with programmable prescaler division of
1 to 256.
— second time base clocked by external signal with programmable prescaler division from 1 to
64.
— second time base external clock source can be replaced by system clock divided by 8.
— both time bases can be exported or imported via Shared Time and Counter bus.
— second time base counter can work as an Angle counter, enabling angle based applications to
match angle instead of time.
— second time base can also be used as a pulse accumulator gated by external signal.
• Event-Triggered VLIW processor (microengine):
— 2 stage pipeline implementation (fetch and execution), with separate instruction memory -
SCM - and data memory - SDM (Harvard architecture)
— fixed-length instruction execution in two system clock microcycle
— interleaved SCM access in dual eTPU Engine avoids contention in time for instruction memory
— SCM address space of up to 16K positions (64 Kbytes)
— SDM with interleaved access in dual eTPU Engine avoids contention for data memory
— SDM address space of up to 8 Kbytes (both Engines).
— instruction set with embedded Channel support, including specialized Channel control
subinstructions and conditional branching on Channel-specific flags.
— channel-oriented addressing: channel-bound address mode with Host configured Channel Base
Address allows channel data isolation, independent of microengine application code.
— channel-bound data address space of up to 128 32-bit parameters (512 bytes)
29-8
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor