PXR40RM Datasheet, PDF (47/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Introduction
• Supports a 64-bit data bus width at the system bus port for CPU loads, DMA transfers and CPU
instruction fetch
— Byte, halfword, word, and doubleword reads are supported
— Only aligned word and doubleword writes are supported
• Hardware and software configurable read and write access protections on a per-master basis
• Pipelined interface to the flash memory array controller allowing overlapped accesses to proceed
in parallel for interleaved or pipelined flash memory array designs
• Configurable access timing allowing use in a wide range of system frequencies
• Multiple-mapping support and mapping-based block access timing (0–31 additional cycles)
allowing use for emulation of other memory types
• Software programmable block program/erase restriction control
• ECC with single-bit correction, double-bit detection
• Minimum program size is two consecutive 32-bit words, aligned on a 0-modulo-8 byte address
(due to ECC)
• Embedded hardware program and erase algorithm
• Erase suspend, program suspend and erase-suspended program
• Shadow information stored in non-volatile shadow block
• Independent program/erase of the shadow block
1.2.5 General-purpose static RAM (SRAM)
The PXR40 SRAM module provides an internal general-purpose 256 KB memory block. The SRAM
controller includes these features:
• Supports read/write accesses mapped to the SRAM memory from any master
• 32 KB block powered by separate supply for standby operation (contents retained)
• Byte, halfword, word, and doubleword addressable
• ECC performs single-bit correction, double-bit detection on 64-bit data elements
• ECC single-bit error corrections are optionally visible to software
1.2.6 Error correction status module (ECSM)
The error correction status module (ECSM) provides the following:
• Status information regarding platform memory errors reported by error detection code (EDC) and
error correcting code (ECC) hardware
— Single-bit correction reporting for SRAM and flash memory
— Multi-bit error reporting
• Includes facilities to allow CPU software to test the error ECC and EDC operation for on-chip
memories by supporting injection of arbitrary error patterns
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
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