PXR40RM Datasheet, PDF (527/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Direct Memory Access Controller (eDMA)
— An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
— Explicit software initiation
— Initiation via a channel-to-channel linking mechanism for continuous transfers
— Peripheral-paced hardware requests (one per channel)
All three methods require one activation per execution of the minor loop
• Support for fixed-priority and round-robin channel arbitration
• Support for complex data structures
• Support to cancel transfers via software
• Channel completion reported via optional interrupt requests
— One interrupt per channel, optionally asserted at completion of major iteration count
— Error terminations are optionally enabled per channel and logically summed together to form
a single error interrupt (32-channel eDMA) or two error interrupts (64-channel eDMA).
• Support for scatter-gather DMA processing
• Support for complex data structures
• Any channel can be programmed to be suspended by a higher priority channel’s activation, before
completion of a minor loop.
21.1.3 Modes of Operation
There are two main operating modes of eDMA: normal mode and debug mode. These modes are briefly
described in this section.
21.1.3.1 Normal Mode
In normal mode, the eDMA is used to transfer data between a source and a destination. The source and
destination can be a memory block or an I/O block capable of operation with the eDMA.
21.1.3.2 Debug Mode
In debug mode, the eDMA does not accept new transfer requests when its debug input signal is asserted.
If the signal is asserted during transfer of a block of data described by a minor loop in the current active
channel’s TCD, the eDMA continues operation until completion of the minor loop.
21.2 External Signal Description
The eDMA has no external signals..
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
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