PXR40RM Datasheet, PDF (1098/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
a13 ^carry
b12 a12
b11 a11
b10 ..
.. ...
... a3
b2 a2
+
b1
------------------------------------------
s12 s11 s10 ... ... s2 s1
Figure 27-72. RSD Adder
27.7.9.1.4 Variable Gain Amplification (VGA) for Pre-gain
The VGA starts after sampling completes. It is enabled by a 2-bit signal PRE_GAIN described in
Section 27.6.3.6, Alternate Configuration 1-8 Control Registers (ADC_ACR1-8).
The ADC takes 2, 8, 64 or 128 clock cycles to do sampling which is selected by the LST[0:1] field in the
conversion command message. After the sampling, if 2x VGA is enabled, there is a 2x gain stage without
comparison before the regular conversion cycles. When 4x VGA is enabled, there are the 2x gain stage
without comparison by 2 times before the normal conversion processing.
27.8 Initialization/Application Information
27.8.1 Multiple Queues Control Setup Example
This section provides an example of how to configure multiple CQueues. Table 27-46 describes how each
CQueue can be used for a different application. Also documented in this section are general guidelines on
how to initialize the on-chip ADCs and the external device, and how to configure the CQueues and the
EQADC.
Table 27-46. Application of Each CQueue
CQueue
Number
0
1
2
CQueue Type
Running Speed
Very fast burst
every 2 s for 200 s;
time-based CQueue pause for 300 s and then
repeat
Fast
hardware-triggered
CQueue
every 900 s
Fast repetitive
time-based CQueue
every 2 ms
Number of
Contiguous
Conversions
2
3
8
Example
Injector current profiling
Current sensing of PWM
controlled actuators
Throttle position
27-116
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor