PXR40RM Datasheet, PDF (943/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Serial Communication Interface (eSCI)
Table 26-11. eSCI_IFSR2 Field Descriptions
Field
RXRDY
TXRDY
LWAKE
STO
PBERR
CERR
CKERR
FRC
UREQ
OVFL
Description
Receive Data Ready Interrupt Flag. This interrupt flag is set when the payload data of a received frame was
transferred into the LIN Receive Register (eSCI_LRR).
Transmit Data Ready Interrupt Flag. This interrupt flag is set when the content of the LIN Transmit Register
(eSCI_LTR) was process by the LIN PE either to generate a frame header or to transmit frame data.
LIN Wakeup Received Interrupt Flag. This interrupt flag is set when a LIN Wakeup character was received, as
described in Section 26.4.6.6, LIN Wakeup.
Slave Timeout Interrupt Flag. This interrupt flag is set when a Slave-Not-Responding-Error is detected. A
detailed description is given in Section 26.4.6.5.5, Slave-Not-Responding-Error Detection.
Physical Bus Error Interrupt Flag. This interrupt flag is set when the receiver input remains unchanged for at least
31 RCLK clock cycles after the start of a byte transmission, as described in Section 26.4.6.5, LIN Error
Reporting.
CRC Error Interrupt Flag. This interrupt flag is set when an incorrect CRC pattern was detected for a received
LIN frame.
Checksum Error Interrupt Flag. This interrupt flag is set when a checksum error was detected for a received LIN
frame.
Frame Complete Interrupt Flag. This interrupt flag is set when a LIN TX frame has been completely transmitted
or a LIN RX frame has been completely received.
Unrequested Data Received Interrupt Flag. This interrupt flag is set when unrequested activity has been
detected on the LIN bus, as described in Section 26.4.6.5, LIN Error Reporting.
Overflow Interrupt Flag. This interrupt flag is set when an overflow as described in Section 26.4.6.5.8, Overflow
Detection was detected.
26.3.2.7 LIN Control Register 1 (eSCI_LCR1)
eSCI_BASE + 0x000C
0
1
2
3
4
5
6
7
8
9
10
11
12
R
0
LRES
W
WU
WUD
0
0
PRTY LIN RXIE TXIE WUIE STIE PBIE
Reset 0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 26-8. LIN Control Register 1 (eSCI_LCR1)
Write: Anytime
13
14
15
CIE CKIE FCIE
0
0
0
This register provides control bits to control and configure the LIN hardware. This register provides the
interrupt enable bits for the interrupt flags in Interrupt Flag and Status Register 2 (eSCI_IFSR2).
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
26-15