PXR40RM Datasheet, PDF (429/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
13.9.19 Embedded Floating-point Round Interrupt (IVOR34)
The Embedded Floating-point Round interrupt is taken when a EFPU floating-point instruction generates
an inexact result and inexact exceptions are enabled.
Table below lists register settings when a EFPU Floating-point Round interrupt is taken.
Table 13-33. Embedded Floating-point Round Interrupt—Register Settings
Register
Setting Description
SRR0
SRR1
MSR
ESR
MCSR
DEAR
Vector
Set to the effective address of the instruction following the excepting EFPU instruction.
Set to the contents of the MSR at the time of the interrupt
UCLE 0
SPE 0
WE 0
CE —
EE 0
PR 0
FP 0
ME —
FE0 0
DE —
FE1 0
IS 0
DS 0
PMM 0
RI —
SPE, [VLEMI]. All other bits cleared.
Unchanged
Unchanged
IVPR_0:15 || IVOR34_16:27 || 4b0000
13.9.20 Performance Monitor Interrupt (IVOR35)
The PXR40 provides a performance monitor interrupt that may be generated by an enabled condition or
event. An enabled condition or event is as follows:
A PMCx register overflow condition occurs with the following settings:
• PMLCax_CE = 1; that is, for the given counter the overflow condition is enabled.
• PMCx_OV = 1; that is, the given counter indicates an overflow.
For a performance monitor interrupt to be signaled on an enabled condition or event, PMGC0_PMIE must
be set.
Although an exception condition may occur with MSR_EE = 0, the interrupt cannot be taken until
MSR_EE = 1.
Table below lists register settings when an performance monitor interrupt is taken.
Table 13-34. Performance Monitor Interrupt—Register Settings
Register
Setting Description
SRR0
SRR1
Set to the effective address of the next instruction to be executed.
Set to the contents of the MSR at the time of the interrupt
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
13-41