PXR40RM Datasheet, PDF (892/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
communications are through a SPI-like protocol.Specifically in the TSB configuration, the DSPI can
serialize up to 32 Parallel Input signals or 32 registered bits.
The DSPI has three configurations:
• SPI Configuration in which the DSPI operates as a basic SPI or a queued SPI.
• DSI Configuration in which the DSPI serializes and deserializes Parallel Input/Output signals or
bits from memory mapped registers.
• CSI Configuration in which the DSPI combines the functionality of the SPI and DSI
configurations.
The DCONF field in the DSPI Module Configuration Register (DSPI_MCR) determines the DSPI
Configuration. See Table 25-5 for the DSPI configuration values.
The DSPI_CTAR0 - DSPI_CTAR7 registers hold clock and transfer attributes. The SPI configuration can
select which CTAR to use on a frame by frame basis by setting a field in the SPI command. The DSI
configuration statically selects which CTAR to use. In CSI Configuration priority logic determines if SPI
data or DSI data is transferred. The type of data transferred dictates which CTAR register the CSI
configuration will use. See Section 25.3.2.3, DSPI Clock and Transfer Attributes Registers 0–7
(DSPI_CTAR0–DSPI_CTAR7), for information on the fields of the DSPI_CTAR registers.
The 16-bit shift register in the Master and the 16-bit shift register in the Slave are linked by the SOUT and
SIN signals to form a distributed 32-bit register. The Master and Slave use 16-bit shift registers regardless
the TSBC bit is asserted in the DSPI_DSICR register. When a data transfer operation is performed, data
is serially shifted a predetermined number of bit positions. Because the registers are linked, data is
exchanged between the Master and the Slave; the data that was in the Master’s shift register is now in the
shift register of the Slave, and vice versa. At the end of a transfer, the TCF bit in the DSPI_SR is set to
indicate a completed transfer. Figure 25-18 illustrates how Master and Slave data is exchanged.
DSPI Master
Shift Register
Baud Rate
Generator
SIN
SOUT
SCK
PCSx
SOUT
SIN
SCK
DSPI Slave
Shift Register
SS
Figure 25-18. SPI and DSI Serial Protocol Overview
The DSPI has eight Peripheral Chip Select (PCS) signals that are used to select which of the Slaves to
communicate with.
The three DSPI configurations share transfer protocol and timing properties so they are described
independently of the configuration in Section 25.4.7, Transfer Formats. The transfer rate and delay settings
are described in Section 25.4.6, DSPI Baud Rate and Clock Delay Generation.
See Section 25.4.11, Power Saving Features, for information on the power-saving features of the DSPI.
25-32
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor