PXR40RM Datasheet, PDF (1008/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Table 27-12. EQADC_FISRx Field Description
Field
0
NCFx
Description
Non-Coherency Flag. NCFx is set whenever a command sequence being transferred through CFIFOx becomes
non coherent. If EQADC_IDCR[NCIEx] and NCFx are asserted, an interrupt request will be generated. Write “1”
to clear NCFx. Writing a “0” has no effect. For more information refer to Section 27.7.4.7.5, Command Sequence
Non-Coherency Detection.
1
TORFx
0 Command sequence being transferred by CFIFOx is coherent.
1 Command sequence being transferred by CFIFOx became non-coherent.
Trigger Overrun Flag for CFIFOx. TORFx is set when trigger overrun occurs for the specified CFIFO in edge or
level trigger mode. Trigger overrun occurs when an already triggered CFIFO receives an additional trigger. When
EQADC_IDCR[TORIEx] and TORFx are asserted, an interrupt request will be generated.
Apart from generating an independent interrupt request for a CFIFOx Trigger Overrun event, the EQADC also
provides a combined interrupt at which the Result FIFO Overflow Interrupt, the Command FIFO Underflow
Interrupt, and the Command FIFO Trigger Overrun Interrupt requests of ALL CFIFOs are ORed. When RFOIEx,
CFUIEx, and TORIEx are all asserted, this combined interrupt request is asserted whenever one of the following
18 flags becomes asserted: RFOFx, CFUFx, and TORFx (assuming that all interrupts are enabled). See
Section 27.7.8, EQADC DMA/Interrupt Request, for details.
Write “1” to clear the TORFx bit. Writing a “0” has no effect.
0 No trigger overrun occurred.
1 Trigger overrun occurred.
Note: The trigger overrun flag will not set for CFIFOs configured for software trigger mode.
2
Pause Flag x. PF behavior changes according to the CFIFO trigger mode. In edge trigger mode, PFx is set when
PFx the EQADC completes the transfer of an entry with an asserted Pause bit from CFIFOx. In level trigger mode, when
CFIFOx is in TRIGGERED status, PFx is set when CFIFO status changes from TRIGGERED due to the detection
of a closed gate. An interrupt routine, generated due to the asserted PF, can be used to verify if a complete scan
of the CQueue was performed. If a closed gate is detected while no command transfers are taking place, it will
have immediate effect on the CFIFO status. If a closed gate is detected while a command transfer to an on-chip
CBuffer is taking place, it will only affect the CFIFO status when the transfer completes. The transfer of entries
bound for the on-chip ADCs is considered completed when they are stored in the appropriate CBuffer.
If EQADC_IDCR[PIEx] and PFx are asserted, an interrupt will be generated. Write “1” to clear the PFx. Writing a
“0” has no effect. Refer to Section 27.7.4.7.3, Pause Status, for more information on the Pause Flag.
0 Entry with asserted PAUSE bit was not transferred from CFIFOx (CFIFO in edge trigger mode), or CFIFO status
did not change from TRIGGERED due to detection of a closed gate (CFIFO in level trigger mode).
1 Entry with asserted PAUSE bit was transferred from CFIFOx (CFIFO in edge trigger mode), or CFIFO status
changes from TRIGGERED due to detection of a closed gate (CFIFO in level trigger mode).
Note: In edge trigger mode, an asserted PFx only implies that the EQADC has finished transferring a command
with an asserted PAUSE bit from CFIFOx. It does not imply that result data for the current command and for
all previously transferred commands has been returned to the appropriate RFIFO.
Note: In software or level trigger mode, when the EQADC completes the transfer of an entry from CFIFOx with an
asserted PAUSE bit, PFx will not be set and transfer of commands will continue without pausing.
27-26
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor