PXR40RM Datasheet, PDF (392/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Core (e200z7) Overview
USER Mode Programmer’s Model Registers
General Registers
Condition Register
CR
General-Purpose
Registers
Count Register
CTR
SPR 9
Link Register
GPR0
GPR1
LR
XER
SPR 8
GPR31
XER
SPR 1
Accumulator
ACC
Timers (Read only)
Time Base
TBL
SPR 268
TBU
SPR 269
Control Registers
SPR General (Read-only)
SPRG4 SPR 260
SPRG5 SPR 261
SPRG6 SPR 262
SPRG7 SPR 263
User SPR
USPRG0 SPR 256
Cache Register (Read-only)
Cache Configuration
L1CFG0 SPR 515
L1CFG1 SPR 516
APU Registers
SPE/EFPU APU Status
and
Control Register
SPEFSCR SPR 512
Debug
DEVENT
DDAM
SPR 975
SPR 576
13.3 Cache
This section lists the most commonly used registers, instructions, and features of Cache. For a complete
listing of all registers and features refer to z759n3 Core Reference Manual.
13.3.1 Cache Overview
The PXR40 supports a pair of 16Kbyte, 4-way set-associative, split instruction and data caches with a
32-byte line size. The caches improve system performance by providing low-latency data to the PXR40
instruction and data pipelines, which decouples processor performance from system memory performance.
The caches are virtually indexed and physically tagged.
Instruction and data addresses from the processor to the caches are virtual addresses used to index the
cache array. The MMU provides the virtual to physical translation for use in performing the cache tag
compare. If the physical address matches a valid cache tag entry, the access hits in the cache. For a read
operation, the cache supplies the data to the processor, and for a write operation, the data from the
processor updates the cache. If the access does not match a valid cache tag entry (misses in the cache) or
a write access must be written through to memory, the cache performs a bus cycle on the system bus.
13-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor