PXR40RM Datasheet, PDF (781/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
The A1 load signal is generated based on the detection of the internal counter reaching 0x00_0001 and has
the duration of one system clock cycle. During the load pulse, A1 still holds its previous value. It is updated
at the second system clock cycle only. Thus, A1 is updated with A2 value at the same time that the counter
(EMIOS_CCNTR[n]) is loaded with 0x00_0001. The load signal pulse has the duration of one system
clock period. If A2 is written within cycle (n), its value is available at A1 at the first clock of cycle (n + 1)
and the new value is used for match at cycle (n + 1). The update disable bits OU[n] of the EMIOS_OUDR
register can be used to control the update of this register, thus allowing the A1 register update to be delayed
for synchronization purposes.
Prescaler Ratio = 2
Internal Counter
0x000008
0x000006
0x000004
0x000002 ₁
0x000001
Counter = A1
Cycle n
Write to A2
Cycle n + 1
A1 match
A1 match
Write to A2
8
4
Cycle n + 2
A1 match
6
Time
A1 Load Signal
A1 Value 0x000008
0x000004
0x000006
A2 Value 0x000008
0x000004
0x000006
Figure 23-36. MCB Mode A1 Register Update in Up Counter Mode
Figure 23-37 shows the A1 register update in up/down counter mode. Note that A2 can be written at any
time within cycle (n) in order to be used in cycle (n + 1). Thus A1 receives this new value at the next cycle
boundary. The update disable bits (OU[n] in EMIOS_OUDR) can be used to disable the update of A1
register.
Prescaler Ratio = 2
EMIOS_CCNTR[n]
Cycle n
A1 Match
Write to A2
Cycle n + 1
A1 Match
Write to A2
Cycle n + 2
0x000006
0x000005
0x000001
Selected Counter = 2
Time
A1 Load Signal
A2 Value ^0x000006
0x000005
0x000006
A1 Value 0x000006
0x000005
0x000006
Figure 23-37. MCB Mode A1 Register Update in Up/Down Counter Mode
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-41