PXR40RM Datasheet, PDF (1210/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
29.2.10 Channel Configuration and Control Registers
Each channel has a group of 3 registers used to control, configure and check status of that channel as shown
in Table 29-13. This organization eases individual channel management.
NOTE
A bus error is issued on read or write accesses to these registers when
ETPUECR bit MDIS=1. Writes are ineffective on bus error.
Table 29-13. Channel Registers Structure
Channel
Offset
Register Name
0x00
0x04
0x08
0x0C
ETPUCxCR - eTPU Channel Configuration Register
ETPUCxSCR - eTPU Channel Status/Control Register
ETPUCxHSRR - eTPU Channel Host Service Request Register
Reserved
One contiguous area is used to map all channel registers of each eTPU engine as shown inTable 29-14.
Table 29-14. Channel Registers Map
Offset
0x400
0x410
0x420
0x430
0x5E0
0x5F0
0x600
Registers Structure
eTPU A Channel 0 Registers Structure
eTPU A Channel 1 Registers Structure
eTPU A Channel 2 Registers Structure
.
.
eTPU A Channel 30 Registers Structure
eTPU A Channel 31 Registers Structure
Reserved
0x800
0x810
0x820
0x9E0
0x9F0
0xA00
eTPU B Channel 0 Registers Structure
eTPU B Channel 1 Registers Structure
.
.
eTPU B Channel 30 Registers Structure
eTPU B Channel 31 Registers Structure
Reserved
There are 64 structures defined, one for each available channel in the eTPU System (32 for each Engine).
The base address for the structure presented can be calculated by using the following equation:
Channel_Register_Base = ETPU_Engine_Channel_Base + (channel_number * 0x10)
where:
ETPU_Engine_Channel_Base = ETPU_Base + 0x400 for Engine 1
ETPU_Engine_Channel_Base = ETPU_Base + 0x800 for Engine 2
29-42
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor