PXR40RM Datasheet, PDF (223/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
GPDI address for a particular pin is the GPIO number plus an offset of SIU_BASE + 0x0800. Gaps exist
in the memory where GPIO pins are not implemented in the package.
Software reads the SIU_GPDIn registers to get the input state of the external GPIO pin. Each GPDI
register contains the input state of one external GPIO pin. If a GPDI register is configured as output, and
the input buffer enable bit is set to one in the PCR register, the SIU_GPDIn register reflects the state of the
output pin.
Address: SIU_BASE + 0x0800 + n
Read Only
0
1
2
3
4
5
6
7
R0
0
0
0
0
0
0 PDIn
W
Reset 0
0
0
0
0
0
0
0
Figure 7-16. General Purpose Data Input (GPDI) Registers 0–255 (SIU_GPDIn)
Field
0–6
7
PDIn
Table 7-24. SIU_GPDI Bit Field Descriptions
Description
Reserved
Pin data in. This bit reflects the input state on the external GPIO pin for the register.
If PCRn[IBE] = 1, then:
0 Signal on pin is a logic 0.
1 Signal on pin is a logic 1.
7.3.1.16 External IRQ Input Select Register (SIU_EIISR)
The SIU_EIISR selects the source for the external interrupt/DMA inputs.
Address: SIU_BASE + 0x0904
0
1
2
3
R
ESEL15
W
ESEL14
Reset 0
0
0
0
4
5
ESEL13
0
0
6
7
ESEL12
0
0
Access: R/W
8
9 10 11 12 13 14 15
ESEL11
ESEL10
ESEL9
ESEL8
0
0
0
0
0
0
0
0
16 17
R
ESEL7
W
Reset 0
0
18 19 20 21 22 23 24 25 26 27 28 29
ESEL6
ESEL5
ESEL4
ESEL3
ESEL2
ESEL1
0
0
0
0
0
0
0
0
0
0
0
0
Figure 7-17. External IRQ Input Select Register (SIU_EIISR)
30 31
ESEL0
0
0
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
7-41