PXR40RM Datasheet, PDF (1203/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Time Processing Unit (eTPU2)
0x200
0x26C
0x400
0x600
0x800
0xA00
Global Channel Registers
Reserved
Engine 1 Channel Registers
Reserved
Engine 2 Channel Registers
Reserved
Figure 29-14. Channel Registers Area
29.2.9 Global Channel Registers
The registers in this section group, by type, the interrupt status and enable bits from all the channels. This
organization eases management of all channels or groups of channels by a single interrupt handler routine.
These bits, except the service and watchdog status, are mirrored in the individual channel registers,
grouped by channel.
29.2.9.1 ETPUCISR - eTPU Channel Interrupt Status Register
Host interrupt status (see Section 29.3.2.2, Interrupts and Data Transfer Requests) from all channels are
grouped in ETPUCISR. Their bits are mirrored from the Channel Status/Control registers (see
Section 29.2.10, Channel Configuration and Control Registers) and Host must write 1 to clear a status bit.
eTPU A: Base + 0x200 / eTPU B: Base + 0x204
R
W
RESET:
0
CIS3
1
CIC3
1
0
1
CIS3
0
CIC3
0
0
2
CIS2
9
CIC2
9
0
3
CIS2
8
CIC2
8
0
4
CIS2
7
CIC2
7
0
5
CIS2
6
CIC2
6
0
6
CIS2
5
CIC2
5
0
7
CIS2
4
CIC2
4
0
8
CIS2
3
CIC2
3
0
9
CIS2
2
CIC2
2
0
10
CIS2
1
CIC2
1
0
11
CIS2
0
CIC2
0
0
12
CIS1
9
CIC1
9
0
13
CIS1
8
CIC1
8
0
14
CIS1
7
CIC1
7
0
15
CIS1
6
CIC1
6
0
R
W
RESET:
16
CIS1
5
CIC1
5
0
17
CIS1
4
CIC1
4
0
18
CIS1
3
CIC1
3
0
19
CIS1
2
CIC1
2
0
20
CIS1
1
CIC1
1
0
21
CIS1
0
CIC1
0
0
22
CIS9
CIC9
0
23
CIS8
CIC8
0
24
CIS7
CIC7
0
25
CIS6
CIC6
0
26
CIS5
CIC5
0
27
CIS4
CIC4
0
28
CIS3
CIC3
0
29
CIS2
CIC2
0
30
CIS1
CIC1
0
31
CIS0
CIC0
0
Figure 29-15. ETPUCISR Register
CISx — Channel x Interrupt Status
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
29-35