PXR40RM Datasheet, PDF (1037/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
Inside EQADC
ADC
To CBuffer
ADCs
Abort
Cont
DMA or interrupt requests
DMA Transaction
Done Signals
FIFO Control
Unit
CFIFOx
Host CPU
or
DMAC
System Memory
CQueuey
32 bits
32 bits
CFIFO Header
NOTE: x=0, 1, 2, 3, 4, 5
y=0, 1, 2, 3, ...
Command Message
ADC Command
Figure 27-42. Command Flow during EQADC operation
ADC commands sent to the on-chip CBuffers are executed in a first-in-first-out basis with exception when
the immediate conversion command function is enabled. Three types of results can be expected: data read
from an ADC register, a conversion result, or a time stamp.
NOTE
While the EQADC pops commands out from a CFIFO, it also is checking
the number of entries in the CFIFO and generating requests to fill it. The
process of pushing and popping commands to and from a CFIFO can occur
simultaneously. However, this is not true for CFIFO0 when configured to
operate in streaming mode for popping.
The FIFO Control Unit expects all incoming results to be shaped in a predefined Result Message format.
Figure 27-43 shows how result data flows inside the EQADC system. Results generated on the on-chip
ADCs are adjusted considering the selected resolution of the ADC and are formatted into result messages
inside the Result Format and Calibration Sub-Block. This result message can be routed directly to one of
the RFIFOs or to an on-chip companion module (decimation filter) via the parallel side interface. After the
data is processed by the companion module, it can be routed back to one of the RFIFOs via the side
interface with the correct format. A result message is composed of an RFIFO header and an ADC Result.
The FIFO Control Unit decodes the information contained in the RFIFO header to determine the RFIFO
to which the ADC result should be sent. Once in an RFIFO, the ADC result is moved to the corresponding
RQueue by the host CPU or by the DMAC as they respond to interrupt and DMA requests generated by
the EQADC. The EQADC generates these requests whenever an RFIFO has at least one entry.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
27-55