PXR40RM Datasheet, PDF (1140/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Decimation Filter
When the filter is bypassed (DECFILT_x_MCR[FTYPE] = 0b00) or in disable mode, the data from the
input buffer is transferred to the output buffer, if it is not already full. If the output buffer is full, the input
buffer is loaded, and another word of input data is sent, then an input overrun occurs.
28.3.2 Decimation Filter Output
NOTE
Decimation Filter H is not writeable or readable from the eQADC, only by
DMA or the CPU. All other decimation filters have no limitations.
The Decimation Filter can send filtered results directly to an eQADC, or to the CPU using the memory
mapped DECFILT_x_OB output buffer register. The output destination for the filter result is determined
by the DECFILT_x_MCR[IO_SEL] field. The filter result is written to the output buffer register when the
decimation count is reached (either an eQADC or CPU destination). The DECFILT_x_MSR[ODF] flag
bit is set when the output buffer is updated. When an eQADC is selected for the result destination, the
result is automatically transferred to an eQADC RFIFO when the output buffer is updated.
The output buffer is not updated when the Decimation Filter is in prefill mode, so the
DECFILT_x_MSR[ODF] flag is not set in that case.
An interrupt or DMA request can be generated when the output buffer is updated, and the output result
destination is the CPU or DMA. A DMA request is generated when the DECFILT_x_MCR[DSEL] = 1,
and the output buffer is updated. If DMA is not enabled, an interrupt is generated by setting the
DECFILT_x_MCR[OBIE] = 1. If both an interrupt and DMA request are enabled, the DMA takes
precedence.
When the filter is bypassed (DECFILT_x_MCR[FTYPE]=0b00), and the eQADC is selected as the output
destination, the data written into the input buffer is delayed until the output buffer is empty and then written
to the output buffer. When the filter is bypassed and the memory mapped register is selected as the output
destination, the data written into the input buffer is immediately written into the output buffer, and the
DECFILT_x_MSR[ODF] flag is set.
A Soft Reset (DECFILT_x_MSR[SRES]) clears the output buffer, and terminates output data transfer to
the output buffer.
28.3.2.1 Output Buffer Overrun
An output overrun occurs when the output buffer (DECFILT_x_OB) is holding output data (sample or
timestamp) that has not been read and it is overwritten with subsequent data (sample or timestamp). Output
overruns are flagged by the DECFILT_x_MSR[OVR] bit. An output buffer overrun interrupt is enabled
by the DECFILT_x_MCR[ERREN] bit. The output buffer empty condition depends on the mode and
output selection as follows:
• When the output result destination is an eQADC, the output buffer is considered empty when the
filter output transfer to an eQADC RFIFO is complete.
• When the output result destination is the CPU/DMA, the output buffer is considered empty after
the buffer has been read and the DECFILT_x_MSR[ODF] flag is cleared.
Prefill inputs do not cause IIR or FIR output overrun for either output destination selection.
28-26
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor