PXR40RM Datasheet, PDF (1423/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Device Performance Optimization
performance of the application comes at the expense of larger code size. Compilers use a host of features,
such as loop unrolling, function inlining and application profile feedback to make the desired trade-offs
between enhanced performance and minimized code size.
The data in Figure 33-5 shows the effects of compiler optimization on a simple application. In this case,
the Dhrystone benchmark was run under three conditions:
• Optimized for small code size
• Optimized for high performance
• A Trade-off between code size and performance
Although this is an extreme example, it highlights how significant the role of the compiler and linker is in
determining the overall performance of an application.
Performance vs. Code Size
1.2
1
Size Optimized
0.8
Trade-off
0.6
0.4
0.2
Speed Optimized
0
0
0.2
0.4
0.6
0.8
1
1.2
Normalised Code Size
Figure 33-5. Influence of Compiler Settings on Application Performance and Code Size
NOTE
Data measured using Dhrystone version 2.1 run on a Power Architecture
based Powertrain device using a standard commercial compiler.
The compiler optimizations do not necessarily have to be applied to the entire application. Analysis of an
application can identify time critical functions that may subsequently be targeted for performance
optimization, without incurring the impact of optimizing the entire application.
There are several other aspects of the compiler and linker that should be considered. In particular, the use
of Small Data Areas (SDAs, sometimes referred to as Special Data Areas) can make a significant
performance improvement. Refer to compiler documentation for usage guidelines on Small Data Areas.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
33-11