PXR40RM Datasheet, PDF (1308/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

External Bus Interface (EBI)
access), the EBI errors the access on the internal bus and does not start the access (nor assert D_TEA)
externally.
Table 30-20. Misalignment Cases Supported by a 64 bit AMBA EBI (internal bus)
No.¹
Program Size and
byte offset
Address
[29:31]²
Data Bus Byte Strobes³
HSIZE⁴
HUNALIGN⁵
1
Half @0x1,0x9
001
0110_0000
10
1
2
Half @0x3,0xB
011
0001_1000
11
1
3
Half @0x5,0xD
101
0000_0110
10
1
4
Half @0x7, 0xF
111
0000_0001
01⁶
1
-
(2 AHB transfers)
000
1000_0000
00
0
5
Word @0x1,0x9
001
0111_1000
11
1
6
Word @0x2,0xA
010
0011_1100
11
1
7
Word @0x3,0xB
011
0001_1110
11
1
8
Word @0x5,0xD
101
0000_0111
10
1
-
(2 AHB transfers)
000
1000_0000
00
0
9
Word @0x6, 0xE
110
0000_0011
10⁷
1
-
(2 AHB transfers)
000
1100_0000
01
0
10
Word @0x7,0xF
111
0000_0001
10⁶
1
11
(2 AHB transfers)
000
1110_0000
10
1
12 Doubleword @0x4,0x8
100
0000_1111
11⁸
1
-
(2 AHB transfers)
000
1111_0000
10
0
13 Doubleword @0x2,0xA
010
0011_1111
11
1
-
(2 AHB transfers)
000
1100_0000
01
0
14 Doubleword 0x6,0xE
110
0000_0011
11⁷
1
15
(2 AHB transfers)
000
1111_1100
11
1
1 _{Misaligned case number. Only transfers where HUNALIGN=1 are numbered as misaligned cases.}
2 _{Address on internal master AHB bus, not necessarily address on external D_ADD pins.}
3 _{Internal byte strobe signals on AHB bus. Shown with Big-Endian byte ordering in this table, even though}
internal master AHB bus uses Little-Endian byte-ordering (EBI flips order internally).
4 _{Internal signal on AHB bus; 00=8-bits, 01=16 bits, 10=32 bits, 11=64-bits. HSIZE is driven according to the}
smallest aligned container that contains all the requested bytes. This results in extra EBI external transfers in
some cases.
5 _{Internal signal on AHB bus that indicates that this transfer is misaligned (when 1).}
6 _{For this case, the EBI internally treats HSIZE as 00 (1-byte access).}
7 _{For this case, the EBI internally treats HSIZE as 01 (2-byte access).}
8 _{For this case, the EBI internally treats HSIZE as 10 (4-byte access).}
Table 30-21 shows which external transfers are generated by the EBI for the misaligned access cases in
Table 30-20, for each port size.
The number of external transfers for each internal AHB master request is determined by the HSIZE value
for that request relative to the port size. For example, a half-word write to @011 (misaligned case #2) with
16-bit port size results in 4 external 16-bit transfers because the HSIZE is 64-bits. For cases where two or
more external transfers are required for one internal transfer request, these external accesses are considered
part of a “small access” set, as described in Section 30.4.2.6, Small Accesses (Small Port Size and Short
Burst Length).
30-46
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor