PXR40RM Datasheet, PDF (244/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

System Integration Unit (SIU)
Table 7-40. eTSEL0A Bit Field Descriptions (continued)
eTSEL0A
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
eQADC Trigger Input
eTPUA30
eTPUA31
Reserved
Reserved
Reserved
Reserved
eMIOS10 AND PIT2
eMIOS10 AND PIT3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
eMIOS23
7.3.1.21 Decimation Filter Register 1 (SIU_DECFIL1)
The SIU_DECFIL1 register contains four ZSELx and HSELx fields that route selected eTPU outputs to
the ZIR (Zero/Integrate/Read) and Halt inputs for decimation filters A through D. See Chapter 28,
Decimation Filter, for more information on the ZIR and Halt operations in the decimation filter.
Address: SIU_BASE + 0x0928
Access: R/W
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
ZSELA
W
HSELA
ZSELB
HSELB
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ZSELC
W
HSELC
ZSELD
HSELD
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
7-62
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor