PXR40RM Datasheet, PDF (826/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexCAN Module
Table 24-8. FLEXCAN_x_MCR Field Descriptions (continued)
Field
Description
8
SUPV
Supervisor Mode
Although the FlexCAN module provides a differentiation between Supervisor and User access types, all
accesses will be always considered of the Supervisor type. As a consequence, the SUPV bit in the
Module Configuration Register (FLEXCAN_x_MCR) has no effect on the module behavior.
.
1 Affected registers are in Supervisor memory space. Any access without supervisor permission
behaves as though the access was done to an unimplemented register location
9
Reserved
10
WRN_EN
Warning Interrupt Enable
When asserted, this bit enables the generation of the TWRN_INT and RWRN_INT flags in the Error and
Status Register. If WRN_EN is negated, the TWRN_INT and RWRN_INT flags will always be zero,
independent of the values of the error counters, and no warning interrupt will ever be generated.
0 TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
1 TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to  96.
11
MDISACK
Module Disable Acknowledge
This read-only bit indicates that FlexCAN is either in Disable Mode or Stop Mode. Either of these low
power modes can not be entered until all current transmission or reception processes have finished, so
the CPU can poll the MDISACK bit to know when FlexCAN has actually entered low power mode. See
Section 24.4.9.2, Module Disable Mode, and Section 24.4.9.3, Stop Mode, for more information.
0 FlexCAN not in any of the low power modes
1 FlexCAN is either in Disable Mode or Stop mode
12
Reserved
13
Doze Mode Enable
DOZE Doze Mode is not supported on this device. Leave this bit as ‘0’.
0 FlexCAN is not enabled to enter low power mode when Doze Mode is requested
14
SRX_DIS
Self Reception Disable
This bit defines whether FlexCAN is allowed to receive frames transmitted by itself. If this bit is asserted,
frames transmitted by the module will not be stored in any MB, regardless if the MB is programmed with
an ID that matches the transmitted frame, and no interrupt flag or interrupt signal will be generated due
to the frame reception.
0 Self reception enabled
1 Self reception disabled
15
MBFEN
Message buffer filter enable. This bit provides the capability of enabling either individual masking of every
message buffer, or global masking of message buffers.
This bit is provided to support backwards compatibility with previous FlexCAN versions. When this bit is
negated, the following configuration is applied:
• Individual Rx ID masking is disabled. Instead of individual ID masking per MB, FlexCAN uses its
previous masking scheme with FLEXCAN_x_RXGMASK, FLEXCAN_x_RX14MASK and
FLEXCAN_x_RX15MASK.
• The reception queue feature is disabled. Upon receiving a message, if the first MB with a matching ID
that is found is still occupied by a previous unread message, FlexCAN will not look for another matching
MB. It will override this MB with the new message and set the CODE field to ‘0110’ (overrun).
Upon reset this bit is negated, allowing legacy software to work without modification.
0 Individual Rx masking and queue feature are disabled.
1 Individual Rx masking and queue feature are enabled.
16–17 Reserved
24-16
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor