PXR40RM Datasheet, PDF (882/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Deserial Serial Peripheral Interface (DSPI)
Table 25-15. DSPI_RSER Field Descriptions (continued)
Field
Description
12
RFOF_RE
Receive FIFO Overflow Request Enable. The RFOF_RE bit enables the RFOF flag in the DSPI_SR
to generate an interrupt requests.
0 RFOF interrupt requests are disabled
1 RFOF interrupt requests are enabled
13
Reserved, should be cleared.
14
RFDF_RE
Receive FIFO Drain Request Enable. The RFDF_RE bit enables the RFDF flag in the DSPI_SR to
generate a request. The RFDF_DIRS bit selects between generating an interrupt request or a DMA
request.
0 RFDF interrupt requests or DMA requests are disabled
1 RFDF interrupt requests or DMA requests are enabled
15
Receive FIFO Drain DMA or Interrupt Request Select. The RFDF_DIRS bit selects between
RFDF_DIRS generating a DMA request or an interrupt request. When the RFDF flag bit in the DSPI_SR is set, and
the RFDF_RE bit in the DSPI_RSER register is set, the RFDF_DIRS bit selects between generating
an interrupt request or a DMA request.
0 Interrupt request will be generated
1 DMA request will be generated
16–31 Reserved, should be cleared.
25.3.2.6 DSPI PUSH TX FIFO Register (DSPI_PUSHR)
The DSPI_PUSHR provides a means to write to the TX FIFO. Data written to this register is transferred
to the TX FIFO. See Section 25.4.3.4, Transmit First In First Out (TX FIFO) Buffering Mechanism, for
more information. Eight or sixteen bit write accesses to the DSPI_PUSHR will transfer 32 bits to the TX
FIFO.
Address: DSPI_BASE + 0x34
Access: R/W
0
1
2
3
4
5
6
7
8
9
10 11 12
13
14 15
R _CON
WT
CTAS
EOQ
CTCN
T
0
0
0
0 _{PCS PCS PCS PCS PCS PCS}
543210
Reset 0 0 0 0 0
0
0000 0 0 0 0 0 0
16 17 18 19 20
21
22 23 24
25
26
27
28
29
30
31
R
TXDATA
W
Reset 0 0 0 0 0
0
0000 0 0 0 0 0 0
Figure 25-8. DSPI PUSH TX FIFO Register (DSPI_PUSHR)
25-22
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor