PXR40RM Datasheet, PDF (767/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
locked until a EMIOS_CBDR[n] read occurs. If a read of EMIOS_CADR[n] is performed, B1 is updated
with contents of A1 even if the B1 update is locked by a previous EMIOS_CADR[n] read operation.
EDPOL = 1
Read EMIOS_CADR[n]
Read EMIOS_CBDR[n]
B
A
B
A
B
Input Signal¹
Selected
Counter Bus
0x000500
0x001000
0x001100
0x001250
0x001525
0x0016A0
FLAG Set Event
A2 (Captured) Value² 0xxxxxxx
B2 (Captured) Value 0xxxxxxx
A1 Value³ 0xxxxxxx
0x001000
0x001100
0x001000
0x001250
0x001525
0x001250
0x0016A0
B1 Value³ 0xxxxxxx
0x001000
0x001000
0x001250
Notes: 1 After input filter
2 EMIOS_CADR[n] = A2
3 EMIOS_CBDR[n] = B1
Figure 23-19. B1 and A1 Updates at EMIOS_CADR[n] and EMIOS_CBDR[n] Reads
Reading EMIOS_CADR[n] followed by EMIOS_CBDR[n] always provides coherent data. If coherent
data is not required, the sequence of reads should be inverted, and EMIOS_CBDR[n] should be read before
EMIOS_CADR[n]. Even in this case, register B1 updates are blocked after EMIOS_CADR[n] is read.
Therefore, a second EMIOS_CBDR[n] read is required to release the B1 register updates.
23.4.1.1.5 Input Period Measurement (IPM) Mode
The IPM mode (MODE = 000_0101) allows the measurement of the period of an input signal by capturing
two consecutive rising edges or two consecutive falling edges. Successive input captures are done on
consecutive edges of the same polarity. The edge polarity is defined by the EDPOL bit in the
EMIOS_CCR[n] register.
When the first edge of selected polarity is detected, the selected time base is latched into the registers A2
and B2, and the data previously held in register B2 is transferred to register B1. On this first capture the
FLAG line is not set and the values in registers B1 are meaningless. On the second and subsequent
captures, the FLAG line is set and data in register B2 is transferred to register B1.
When the second edge of the same polarity is detected, the counter bus value is latched into registers A2
and B2, and the data previously held in register B2 is transferred to data register B1 and to register A1.
The FLAG bit is set to indicate that the start and end points of a complete period have been captured. This
sequence of events is repeated for each subsequent capture. The EMIOS_CADR[n] and
EMIOS_CBDR[n] registers return the values in the A2 and B1 registers, respectively.
To allow coherent data, reading EMIOS_CADR[n] forces A1 content be transferred to B1 register and
disables transfers between B2 and B1. These transfers are disabled until the next read of the
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
23-27