PXR40RM Datasheet, PDF (708/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

FlexRay Communication Controller (FLEXRAY)
22.6.9.1 Overview
The two receive FIFOs implement the queued message buffer concept defined by the FlexRay
Communications System Protocol Specification, Version 2.1 Rev A. One FIFO is assigned to channel A,
the other FIFO is assigned to channel B. Both FIFOs work completely independent from each other.
The message buffer structure of each FIFO is described in Section 22.6.3.3, Receive FIFO. The area in the
flexray memory for each of the two FIFOs is characterized by:
• The FIFO system memory base address
• The index of the first FIFO entry given by Receive FIFO Start Index Register (RFSIR)
• The number of FIFO entries and the length of each FIFO entry as given by Receive FIFO Depth
and Size Register (RFDSR)
22.6.9.2 FIFO Configuration
The FIFOs can be configured for two different locations of the system memory base address via the FIFO
address mode bit FAM in the Module Configuration Register (MCR).
22.6.9.2.1 Single System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag MCR[FAM] is set to 0. In this mode, the
location of the system memory base address for the FIFO buffers is System Memory Base Address
Register (SYMBADR).
22.6.9.2.2 Dual System Memory Base Address Mode
This mode is configured, when the FIFO address mode flag MCR[FAM] is set to 1. In this mode, the
location of the system memory base address for the FIFO buffers is Receive FIFO System Memory Base
Address Register (RFSYMBADR).
The FIFO control and configuration data are given in Section 22.6.3.7, Receive FIFO Control and
Configuration Data. The configuration of the FIFOs consists of two steps.
The first step is the allocation of the required amount of flexray memory for the FlexRay window. This
includes the allocation of the message buffer header area and the allocation of the message buffer data
fields. For more details see Section 22.6.4, FlexRay Memory Layout.
The second step is the programming of the configuration data register while the PE is in POC:config.
The following steps configure the layout of the FIFO.
• Configure the FIFO update and address modes in Module Configuration Register (MCR)
• Configure the FIFO system memory base address
• Configure the Receive FIFO Start Index Register (RFSIR) with the first message buffer header
index that belongs to the FIFO
• Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO entry size
• Configure the Receive FIFO Depth and Size Register (RFDSR) with FIFO depth
• Configure the FIFO Filters
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PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor