PXR40RM Datasheet, PDF (138/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Power Management Controller (PMC)
5.4 Memory Map/Register Definition
Table 5-3 shows the PMC memory map. The PMC memory maps 3 registers for configuring, monitoring,
and trimming the LVD monitors.
Table 5-3. Power Management Controller Memory Map
Address
Register
Bits Access Reset Value Section/Page
PMC_BASE + 0x0000 PMC_MCR — Configuration register
32
R/W 0x9800_0000
PMC_BASE + 0x0004 PMC_TRIMR — Trimming register
32
R/W 0x0000_0006
PMC_BASE + 0x0008 PMC_SR — Status register
32
R/W 0x0200_0000
or
0x0600_0000¹
1 _{Reset value depends on whether RAM standby regulator switch reported a brownout condition.}
5.4.1/5-6
5.4.2/5-8
5.4.3/5-12
5.4.1 Configuration Register (PMC_MCR)
The configuration register contains configuration and interrupt enable bits for the LVD monitors.
Refer to Section 5.1.1, Features, for a listing of which VDDEH powers are monitored.
Offset: PMC_BASE + 0x0000
Access: User read/write
0
1
2
3
4
5
67
8
9
10
11
12
13 14 15
R
00
0
LVRER LVREH LVRE50 LVRE33 LVREC LVREA
LVIER LVIEH LVIE50 LVIE33 LVIEC LVIEA
TLK
W
Reset 1
0
0
1
1
0 00 0
0
0
0
0
000
16
17
18
R0
0
0
W
Reset 0
0
0
19
20
21 22 23 24
25
26
27
28
29 30 31
0
0
0 00 0
0
0
0
0
000
0
0
0 00 0
0
0
0
0
000
Figure 5-2. Configuration and Status Register (PMC_MCR)
Table 5-4. PMC_MCR Field Descriptions
Field
Description
0
LVRER
Reset-pin-supply low-voltage reset enable. This bit defines whether an LVD assertion on the supply of the I/O
segment that contains the reset pin will generate system reset or not.
0 Disabled. LVD assertion on the supply of the I/O segment that contains the reset pin does not cause system reset.
1 Enabled. LVD assertion on the supply of the I/O segment that contains the reset pin causes system reset.
1
LVREH
VDDEH low-voltage reset enable. This bit defines whether an LVD assertion on any monitored VDDEH supply will
generate system reset or not.
0 Disabled. LVD assertion on any monitored VDDEH supply does not cause system reset.
1 Enabled. LVD assertion on any monitored VDDEH supply causes system reset.
2
LVRE50
VDDREG low-voltage reset enable. This bit defines whether an LVD assertion on the VDDREG supply of the voltage
regulator will generate system reset or not.
0 Disabled. LVD assertion on the VDDREG supply of the voltage regulator does not cause system reset.
1 Enabled. LVD assertion on the VDDREG supply of the voltage regulator causes system reset.
PXR40 Microcontroller Reference Manual, Rev. 1
5-6
Freescale Semiconductor