PXR40RM Datasheet, PDF (1405/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

IEEE 1149.1 Test Access Port Controller (JTAGC)
32.3.2 Bypass Register
The bypass register is a single-bit shift register path selected for serial data transfer between TDI and TDO
when the BYPASS, CLAMP, HIGHZ or reserve instructions are active. After entry into the capture-DR
state, the single-bit shift register is set to a logic 0. Therefore, the first bit shifted out after selecting the
bypass register is always a logic 0.
32.3.3 Device Identification Register
The device identification register, shown in Figure 32-3, allows the part revision number, design center,
part identification number, and manufacturer identity code to be determined through the TAP. The device
identification register is selected for serial data transfer between TDI and TDO when the IDCODE
instruction is active. Entry into the capture-DR state while the device identification register is selected
loads the IDCODE into the shift register to be shifted out on TDO in the Shift-DR state. No action occurs
in the update-DR state.
IR[4:0]: 0_0001 (IDCODE)
Access: R/O
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R PRN
DC
PIN
MIC
ID
W
Reset 0 0 0 0 1 0 0 0 0 0 1 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 1
Figure 32-3. Device Identification Register
Table 32-2. Device Identification Register Field Descriptions
Field
Description
0–3 Part revision number. Contains the revision number of the device. This field changes with each revision of the device
PRN or module.
4–9 Design center. Indicates the Freescale design center. For the MPC5574 this value is 0x20.
DC
10–19 Part identification number. Contains the part number of the device. For the MPC5574, this value is 0x274.
PIN
20–30 Manufacturer identity code. Contains the reduced Joint Electron Device Engineering Council (JEDEC) ID for
MIC Freescale, 0xE.
31 IDCODE register ID. Identifies this register as the device identification register and not the bypass register. Always
ID set to 1.
32.3.4 CENSOR_CTRL Register
The CENSOR_CTRL register is a 64-bit shift register path from TDI to TDO selected when the
ENABLE_CENSOR_CTRL instruction is active. The default reset value of the CENSOR_CTRL register
is 64’b0. The CENSOR_CTRL register transfers its value to a parallel hold register on the rising edge of
TCK when the TAP controller state machine is in the Update-DR state. Once the
ENABLE_CENSOR_CTRL instruction is executed, the register value will remain valid until a JTAG reset
occurs.
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
32-5