PXR40RM Datasheet, PDF (772/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
In order to have coherent data in continuous operation mode, the following steps should be performed,
assuming the FLAG bit is initially cleared:
1. Wait for FLAG assertion.
2. Read the EMIOS_CADR[n] register.
3. Read the EMIOS_CBDR[n] register.
4. Clear the FLAG bit.
5. Return to step #1.
Accumulation cycles may be lost if the read is not performed in a timely manner. Whenever the Overrun
bit is asserted it means that one or more cycles have been lost.
Triggering of the counter clock (input event) is done by a rising or falling edge or both edges on the input
pin. The polarity of the triggering edge is selected by the EDSEL and EDPOL bits in EMIOS_CCR[n]
register.
For continuous mode operation (MODE[6] cleared, MODE[0:6] = 000_1000), the counter is cleared on
the next input event after a FLAG generation and continues to operate as previously described.
For single-shot operation (MODE[6] set, MODE[0:6] = 000_1001), the counter is not cleared or
incremented after a FLAG generation until a new writing operation to register A (EMIOS_CADR) is
performed.
Figure 23-25 and Figure 23-26 show how the unified channel can be used for continuous and single-shot
pulse/edge accumulation mode.
MODE[6] = 0
EMIOS_CCNTR[n]¹
0xFFFFFF
0x001500
Write to A1
A1 Match
A1 Match
0x000000
FLAG Pin/Register
Selected Counter Bus
Input Signal²
A1 Value³
A2 Value⁴
B1 Value
B2 Value⁵
0x000090
Events
0xxxxxxx
0xxxxxxx
0xxxxxxx
0xxxxxxx
0x001500
0x000090
A1 Events
0x000400
0x001000
No Events
0x001500
0x000400
0x000090
0x000400
A1 Events
0x001000
Notes: 1. Cleared on the first input event after writing to register A1
2. After input filter
3. EMIOS_CADR[n] = A1 (when writing)
4. EMIOS_CADR[n] = A2 (when reading)
5. EMIOS_CBDR[n] = B1
Figure 23-25. PEA Continuous Mode Example
0x007000
0x001500
0x007000
0x001000
0x007000
Time
23-32
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor