PXR40RM Datasheet, PDF (1050/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
NOTE
CFIFO0 can be configured to work in an alternative way called Streaming
Mode. This mode is very different from the mode described here because it
maintains some stored commands to execute them several times in sequence
and in loop.
NOTE
Only whole words must be written to EQADC_CFPR. Writing half-words
or bytes to EQADC_CFPR will still push the whole 32-bit CF_PUSH field
into the corresponding CFIFO, but undefined data will fill the areas of
CF_PUSH that were not specifically designated as target locations for
writing.
Figure 27-49 describes the important components in the CFIFO. Each CFIFO is implemented as a circular
set of registers to avoid the need to move all entries at each push/pop operation. The Push Next Data
Pointer points to the next available CFIFO location for storing data written into the EQADC Command
FIFO Push Register. The Transfer Next Data Pointer points to the next entry to be removed from CFIFOx
when it completes a transfer. The CFIFO Transfer Counter Control Logic counts the number of entries in
the CFIFO and generates DMA or interrupt requests to fill the CFIFO. TNXTPTR in EQADC_FISR,
indicates the index of the entry that is currently being addressed by the Transfer Next Data Pointer, and
CFCTR, in the same register, provides the number of entries stored in the CFIFO. Using TNXTPTR and
CFCTR, the absolute addresses for the entries indicated by the Transfer Next Data Pointer and by the Push
Next Data Pointer can be calculated using the following formulas:
Transfer Next Data Pointer Address = CFIFOx_BASE_ADDRESS + TNXTPTRx*4
Push Next Data Pointer Address = CFIFOx_BASE_ADDRESS +
[(TNXTPTRx+CFCTRx) mod CFIFO_DEPTH] * 4
where
• a mod b returns the remainder of the division of a by b.
• CFIFOx_BASE_ADDRESS is the smallest memory mapped address allocated to a CFIFOx entry.
• CFIFO_DEPTH is the number of entries contained in a CFIFO - four in this implementation.
When CFSx in EQADC_CFSR is TRIGGERED, the EQADC generates the proper control signals for the
transfer of the entry pointed by Transfer Next Data Pointer. CFUFx in EQADC_FISR is set when a
CFIFOx underflow event occurs. A CFIFO underflow occurs when the CFIFO is in TRIGGERED state
and it becomes empty. No commands will be transferred from an underflowing CFIFO, nor will command
transfers from lower priority CFIFOs be blocked. CFIFOx is empty when the Transfer Next Data Pointer
x equals the Push Next Data Pointer x and CFCTRx is zero. CFIFOx is full when the Transfer Next Data
Pointer x equals the Push Next Data Pointer x and CFCTRx is not zero.
When the EQADC completes the transfer of an entry from CFIFOx: the transferred entry is popped from
CFIFOx, the CFIFO counter CFCTR in the EQADC_FISR is decremented by one, and Transfer Next Data
Pointer x is incremented by one (or wrapped around) to point to the next entry in the CFIFO. The transfer
of entries bound for the on-chip ADCs is considered completed when they are stored in the appropriate
CBuffer.
27-68
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor