PXR40RM Datasheet, PDF (436/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

AMBA Crossbar Switch (XBAR)
Table 14-2. XBAR Register Memory Map (continued)
Address
Register
Base + 0x0610
XBAR_SGPCR6—General-purpose control
register for slave port 6
Base + (0x0614–0x06FF) Reserved
Base + 0x0700
XBAR_MPR7—Master priority register for
slave port 7
Base + (0x0704–0x070F) Reserved
Base + 0x0710
XBAR_SGPCR7—General-purpose control
register for slave port 7
Base + (0x0714– x07FF) Reserved
Bits Access Reset Value Section/Page
32 R/W 0x0000_0000 14.2.1.2/14-6
32 R/W 0x7654_3210 14.2.1.1/14-4
32 R/W 0x0000_0000 14.2.1.2/14-6
14.2.1 Register Descriptions
There are two registers for each slave port of the XBAR. The registers can only be accessed in supervisor
mode using 32-bit accesses.
The slave SGPCR also features a bit (RO), which when written with a 1, prevents all slave registers for
that port from being written to again until a reset occurs. The registers remain readable, but future write
attempts have no effect on the registers and are terminated with an error response.
14.2.1.1 Master Priority Registers (XBAR_MPRn)
The XBAR_MPR for a slave port sets the priority of each master port when operating in fixed priority
mode. They are ignored in round-robin priority mode unless more than one master has been assigned high
priority by a slave.
NOTE
Masters must be assigned unique priority levels.
The master priority register can only be accessed in supervisor mode with 32-bit accesses. After the read
only (RO) bit is set in the slave general-purpose control register, the master priority register can only be
read. Attempts to write to it have no effect on the MPR and result in an error.
NOTE
XBAR_MPR must be written with a read/modify/write for code
compatibility.
14-4
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor