PXR40RM Datasheet, PDF (1053/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Queued Analog-to-Digital Converter (EQADC)
The purpose of this bit is to mark in the command queue, where to start a repeating sequence. This location
is stored in an additional pointer ‘Repeat Pointer’.
Streaming mode requires 2 trigger inputs. The standard queue 0 trigger, in this mode referred to as Repeat
Trigger and a new internal trigger input to the eQADC called Advance Trigger (no filter available).
CFIFO0 is configured to operate in streaming mode by setting the bit STRME0 as described in
Section 27.6.2.5, EQADC CFIFO Control Registers (EQADC_CFCR). CFIFO0 is eight entries deep in
extended mode by setting the bit CFEEE0 in the same EQADC_CFCR register, and each entry is 32 bits
long. This CFIFO0 serves as a local storage of a few commands that need to be executed sequentially as
in a FIFO but can contain sub-queues that need to be executed several times. The CFFF0 bit in
Section 27.6.2.7, EQADC FIFO and Interrupt Status Registers (EQADC_FISR), is used to assure the
CFIFO0 is not full and command messages are stored from address 0x0 to 0x7.
27.7.4.2.1 CFIFO0 Operation in Streaming Mode
In Streaming mode, the CFIFO0 is filled with CCWs using the DMA exactly the same as existing modes.
The CFIFO executes commands as per the existing modes until it executes a Conversion Command Word
with the Repeat bit set. When this CCW is executed, the Repeat Pointer is set to point to this FIFO location
and from this CCW onwards, CFIFO0 entries is not invalidated, that is, the Repeat Pointer prevents this
and subsequent entries from being overwritten.
The queue continues to execute until a CCW with an asserted Pause bit is completed; then the queue stops
and enters the Pause state, waiting for a trigger. This is the same as normal behavior.
The Pause state is exited in one of two ways: Repeat Trigger or Repeat Trigger with Advance Trigger. The
Repeat trigger with no Advance trigger causes the Transfer Next Data Pointer to be loaded with the Repeat
Pointer location and CCWs are then executed from the Repeat Pointer back to the Pause bit. This means
that a section of the CFIFO0 is repeatedly executed every time a Repeat Trigger occurs.
The Repeat trigger with the Advance trigger pending causes all CCWs from the Repeat pointer to the Pause
bit to be invalidated and the CCW after the pause bit to be executed. This is achieved by invalidating the
Repeat Pointer. The effect is that the queue advances beyond the repeating section of the CFIFO0 to
execute new CCWs.
Note that the Advance trigger can occur at any time between Repeat triggers, but is only actioned when
the next Repeat trigger occurs. Prior to that it is pending.
In a typical application, the queue is made of some configuration commands to the ADC (to flush the
decimator or turn on pad pull-up/down) followed by a repeating section of ADC conversions on one or
more ADC channels from one or more sensors; followed by a few more configuration commands; then
more repeating ADC conversions, until the entire engine cycle is complete; when the queue is restarted.
The mechanism described permits any number of repeating sub-queues to be loaded and executed,
interspersed by configuration commands.
27.7.4.2.2 Triggering Description in Streaming Mode
The additional advance-trigger signal ATRIG0 is detected by a separate circuit that is configured by the
bit field AMODE0 as described in Section 27.6.2.5, EQADC CFIFO Control Registers (EQADC_CFCR).
This trigger signal is used as an advance control of pop pointer of CFIFO0. In addition, it is used as the
Freescale Semiconductor
PXR40 Microcontroller Reference Manual, Rev. 1
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