PXR40RM Datasheet, PDF (782/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Enhanced Modular Input/Output Subsystem (eMIOS200)
23.4.1.1.13 Output Pulse Width and Frequency Modulation (OPWFM) Mode
In the OPWFM mode, the duty cycle of the output signal is the value defined in register A1 plus 0x1, and
the period is the value defined in register B1 plus 0x1. MODE[6] bit controls the transfer from register B2
to B1, which can be done either immediately (MODE[6] cleared, MODE = 00110b0), providing the fastest
change in the duty cycle, or at every match of register A1 (MODE[6] set, MODE = 00110b1).
When OPWFM mode is entered, coming out from GPIO mode, the output flip-flop is set to the
complement of the EDPOL bit in the EMIOS_CCR[n] register.
The internal counter is automatically selected as a time base, therefore the BSL[1:0] bits in register
EMIOS_CCR[n] have no meaning. When a match on comparator A occurs, the output flip-flop is set to
the value of the EDPOL bit. When a match occurs on comparator B, the output flip-flop is set to the
complement of the EDPOL bit and the internal counter is cleared.
FLAG can be generated at match B, when MODE[5] is cleared, or in both matches, when MODE[5] is set.
At any time, the FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on A or B respectively. Also, FORCMB clears the internal counter. Note that
the FLAG bit is not set by the FORCMA or FORCMB operations.
If subsequent comparisons occur on comparators A and B, the PWFM pulses continue to be output,
regardless of the state of the FLAG bit.
In order to achieve 100% duty cycle, both registers A1 and B1 must be set to the same value. When a
simultaneous match occurs on comparators A and B, the output flip-flop is set to the value of EDPOL bit.
0% duty cycle is possible by writing 0x0 to register A (EMIOS_CADR). When a match occurs, the output
flip-flop is set at every period to the complement of EDPOL bit. The transfer from register B2 to B1 is still
controlled by MODE[6] bit.
NOTE
Writing 0x0 to A1 and B1 produces a duty cycle of 0%.
Figure 23-38 shows the unified channel running in OPWFM mode with immediate register update and
Figure 23-39 shows the unified channel running in OPWFM mode with next period update.
23-42
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor