PXR40RM Datasheet, PDF (49/1434 Pages) Freescale Semiconductor, Inc – PXR40 Microcontroller

Introduction
— 6 KB of shared parameter (data) RAM (SPRAM)
• Resource sharing features support channel use of common channel registers, memory and
microengine time
— Hardware scheduler works as a task management unit, dispatching event service routines by
pre-defined, host-configured priority
— Channel context switch time is six system cycles. Each channel has its own context of static
data memory and timer hardware resources consisting of programmable flags, timer control
and status hardware
— SPRAM shared between host CPU and eTPU, supporting communication either between
channels and host or inter-channel
— Dual-parameter coherency hardware support allows atomic access to two parameters by host
— Enhancements to DMA and interrupt structure to allow any channel to assert any interrupt
source or DMA trigger¹
• Test and development support features:
— IEEE-ISTO 5001-2003 standard class 3 compliant for the eTPU (Nexus)
— Data trace via data write messaging and data read messaging
— Ownership trace via ownership trace messaging (OTM)
— Program trace via branch trace messaging
— Watchpoint messaging via the auxiliary port
— SCM continuous signature-check built-in self test (MISC — multiple input signature
calculator), runs concurrently with eTPU normal operation
1.2.9 Software watchdog timer (SWT)
The software watchdog timer (SWT) is a second watchdog module to complement the standard Power
Architecture watchdog integrated in the CPU core. When enabled, the SWT requires periodic execution
of a watchdog servicing sequence. Writing the sequence resets the timer to a specified time-out period. If
this servicing action does not occur before the timer expires the SWT generates an interrupt or hardware
reset. The SWT can be configured to generate a reset or interrupt on an initial time-out, a reset is always
generated on a second consecutive time-out.
The following features are implemented:
• 32-bit time-out register to set the time-out period
• Programmable selection of system or oscillator clock for timer operation
• Programmable selection of window mode or regular servicing
• Programmable selection of reset or interrupt on an initial time-out
• Master access protection
• Hard and soft configuration lock bits
• Reset configuration inputs allow timer to be enabled out of reset
PXR40 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
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